Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Test Bench Development for the Radiation Hard GBTX ASIC

Sep 24, 2014, 5:02 PM
1m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster Radiation Second Poster Session

Speaker

Pedro Vicente Leitao (CERN)

Description

This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements bidirectional 4.8 Gb/s links between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional tests of the GBTX and to evaluate its performance. Total Ionizing Dose and Single-Event Upsets tests were also performed and the results will be presented in this paper.

Summary

The developed test bench consists in a custom build PCB, called the Stand-Alone Test board (SAT board), which allows performing Bit Error Rate (BER) tests on the GBTX ASIC using full data payload. To do so the SAT board hosts the GBTX ASIC, an ALTERA Cyclone V FPGA and the necessary interconnection between both to perform full BER tests. This consists in two SFP+ modules for the high speed 4.8 Gb/s optical link and 40 e-links (80 Mbit, 160 Mbit or 320 Mbit) for the data transmission plus 2 e-links (80 Mbit) for the slow control channel, summing up to 126 differential lines. The necessary GBTX configuration signals are controlled by the Cyclone V, which has firmware capable of acting as a slow control device and as a front-end device with adaptable phase-shifted clocks for input data alignment. The GBT-FPGA latency-optimized firmware is also implemented on Cyclone V in order to emulate an off-detector system. The Cyclone V can produce Pseudo Random Bit Sequence (PRBS) patterns for the BER tests and is controlled via Ethernet using an UDP protocol communication managed by a Graphical User Interface implemented in JAVA.
Automated tests were developed using the SAT board which allowed the automatic performance characterization of several GBTX‘s circuits, such as the xPLL, phase-shifter and clock manager. Total Ionizing Dose (TID) tests were performed using photons (x-ray, CERN) up to 100 Mrad ionizing dose, and results show 16.3% total jitter variation for the SER eye diagram and 12.5% total jitter variation for the phase-shifter at 320 MHz with no degradation of the data transmission performance. Single Event Upsets (SEUs) tests were performed in the Centre de Ressources du Cyclotron, Louvain-la-Neuve, Belgium, in the Heavy Ion Irradiation Facility. The GBTX ASIC was irradiated using high penetration particles (Argon, Neon, Nickel and Krypton) and the measured SEU cross section will be given in the full paper.
This paper aims to report the GBTX ASIC sensitivity to radiation and to help the GBTX ASIC users to integrate the ASIC in their systems.

Primary author

Co-authors

David Porret (CERN) Diego Matos Figueiredo (Universidade do Estado do Rio de Janeiro (BR)) Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part) Ken Wyllie (CERN) Manoel Barros Marin (CERN) Paulo Rodrigues Simoes Moreira (CERN) Rui De Oliveira Francisco (CERN) Sebastian Stefan Feger (CERN) Mrs Sophie Baron (CERN) Tullio Grassi (Univ. of Maryland (USA))

Presentation materials