The LHC clock and triggers distribution systems (typically GBT or TTC) require recovering the timing signals with fixed and deterministic phase and low-jitter. Experience has proved that such functionality cannot be found in Commercially Off-The Shelf components (COTS). Therefore there is no satisfying solution to provide a reliable timing distribution in new designs based on TTC or GBT and users are forced to build workarounds solutions to solve this problem.
We propose a new radiation tolerant ASIC based on the eCDR IP to fulfil several needs: LHC clock recovery for Back-End and Front-End modules, synchronous reference clock generation for GBT-FPGA transceivers, CDRs for TTC decoders in radiation-hard environments (typically used with IGLOO2 FPGAs), clock synthesis for GBTx eLinks …
A radiation-tolerant ASIC (eCDR-PLL) is being designed for LHC clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR) with fixed and determinist phase and with low jitter (<10ps rms). It operates in two FM modes: either generating 40, 120 and 240MHz outputs (for GBT-FPGA applications) or providing 40, 80, 160 and 320 MHz (for TTC and eLinks applications). The CDR operates with 40, 80, 160 or 320Mbit/s data generating in-phase clocks at 40, 80, 160 and 320MHz, regardless of the data rate. All the outputs are phase programmable with a resolution of 195 or 260ps depending on the FM mode.