Speaker
Description
Summary
To keep the CMS level 1 trigger rate at a reasonable level (<= 1 MHz) in the high luminosity phase of the LHC, track information from the silicon trackers will be required. The total data rate of the silicon tracker is in the order of 100 Tbit/s and the data processing must be carried out within 6 µs. Best estimates suggest that the track trigger will be a cutting-edge electronic system consisting of approximately 50 highly packed crates.
We developed a simulation framework that serves as a powerful tool for the evaluation of possible system architectures and trigger algorithms for the track trigger. The framework is based on high-level models of the system components written in SystemC and uses input data from physics simulations which allow the simulation of realistic scenarios. SystemC is a C++ library that extends the programming language's features with the possibility of hardware simulation. SystemC allows a higher abstraction level and a higher simulation performance compared with traditional Hardware Description Languages (HDL), such as VHDL and Verilog. However, modules written in an HDL can be integrated in the SystemC framework and co-simulated within off-the-shelf tools like ModelSim. Hence, the simulation framework acts also as a test bench for digital modules that will be embedded in integrated circuits or FPGAs. Models are as generic as possible, i.e. new ideas could be adapted easily and tested within the framework.
Within the framework, we implemented a fully functional model of the track trigger system that is built of a front-end (FE) part and a back-end (BE) part. On the FE side, the model consists of FE chips which read the coordinates of the hits from an input file and the the data concentrator (DC) chip. The DC chip collects hit data from the 16 FE chips belonging to one detector module, it generates data packets that can absorb data peaks by distributing hit information in several consecutive clock cycles and, finally, it handles the serial transmission to the BE electronics. On the BE side, serial data streams from modules belonging to different detector layers are received by the data organizer that extract hits from DC packets, reconstruct their timing, aggregate them with hits from neighboring detector slices and stores hit data in FIFOs. To cope with the expected hit rate, the data is then distributed to four associative memory (AM) boards that compare the input hit patterns with preloaded patterns in order to find relevant tracks (roads) to be transmitted to the Trigger processor.
On the basis of system elaborated above, we will describe in detail the architecture of the simulation framework and we will present results of simulations performed with physics input data in different configurations (e.g. size of data buffers, link speed). We will present the achieved simulation performance gain by using SystemC in the order of factor ten and how co-simulation has been used to validate the firmware of the AM board controller.
