Speaker
Description
Summary
We have built and installed new front-end trigger electronics for the Cathode Strip Chambers (CSCs) in the CMS Endcap Muon system that will efficiently handle the increased data rate in the forthcoming High Luminosity LHC accelerator upgrade. Optical links operating at 3.2 gb/s carry the cathode strip data from the CSC to the Trigger Motherboard (TMB). The mezzanine card on the TMB supports a Virtex-6 FPGA that is responsible for unpacking the incoming data, looking for muon track patterns across all six layers of cathode strips, and checking them for a coincidence in time with hits from the anode wires. When good track stubs are found that point toward the interaction point, all the information about the muon candidates are sent to the muon first level trigger system. Doing all this in high-pileup conditions requires fast electronics and complex algorithms that minimize dead time and maximize efficiency. We report on the design and recent performance tests of the newly installed trigger system, as well as the development of the new trigger algorithm.
