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The LHC collaborations have performed significant development to consolidate their electronics and online systems for Run 2. These developments aim to efficiently use the LHC luminosity anticipated for the period 2015-2018 and include an increase of the bandwidth available in the online systems.
Two LHC experiments, ALICE and ATLAS, will use the same new card, the ALICE Common Read-Out Receiver Card (C-RORC), configured with experiment-specific firmware, to interface up to twelve digital optical links to the input/output bus (PCIe Gen 2) of the online computers. The ATLAS specific firmware is known as the ROBINNP firmware.
All the information sent by the 18 sub-detectors composing ALICE are currently read out by the data acquisition system using ~ 500 optical links called DDL (Detector Data Link), each one with a maximum throughput of 2.1 Gb/s. ALICE will face a partial upgrade in 2015 to cope with the increased luminosity of the LHC. Two detectors (the Time Projection Chamber and the Transition Radiation Detector) will consolidate their front-end electronics to increase the acquisition rate to 4 and 5 Gb/s respectively. For this reason a new common DAQ and HLT (High-Level Trigger) readout card has been developed with a higher input link capability - 12 links (using three QSFP transceivers) instead of 2 - and a faster PCIe interface (an eight-lane PCIe Gen 2 instead of Gen 1). The protocol used to send data is still the same but the links run at a higher speed, up to a maximum of 6 Gb/s per link.
The off-detector read-out chain of the ATLAS experiment, consists of sub-detector specific Read-Out Drivers (RODs), which output event fragments to the Read-Out System (ROS) via point-to-point optical Read-Out Links (ROLs). In Run 1 the ROS was implemented with 4U high rack-mountable server-class PCs, each equipped with up to four custom 64-bit PCI cards, the ROBINs. For Run 2 the ROS will use 2U PCs, each with two C-RORCs running ROBINNP firmware providing the ROBIN functionality. The firmware currently implements a PCIe x8 Gen 1 interface, which supports read-out of more than the required 50% of all data input on 12 ROLs running at 200 MB/s. After an upgrade to Gen 2 100% read-out could be possible.
A single Xilinx Virtex-6 series FPGA handles data input from the 12 optical links and buffering in the on-board DDR3 memory. It is also capable of doing on-the-fly data processing and initiating DMA transfer of event data directly from the links or from the on-board memory to the PC memory. The common use of the same complex hardware demonstrates the flexibility of programmable logic to implement different protocols satisfying the different requirements of two experiments.
