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Description
Summary
VMM is a family of 64-channel high-functionality front-end ASICs being developed for the ATLAS Muon upgrade. We present the second prototype called VMM2, which is an evolution of VMM1 but with a much higher complexity and functionality. The step-up can be appreciated from the increase in layout size (from 5.9×8.4 mm² to 13.5×8.4 mm²) and transistor count (from ~500 thousand to ~5 million).
Each channel integrates a charge amplifier with adjustable polarity a third-order DDF filter with adjustable peaktime in four values (25-200ns), stabilized baseline and adjustable gain in eight values (0.5-16 mV/fC). It follows a sub-hysteresis discriminator with neighbor logic and threshold trimming, a peak and time detector. The neighbor logic forces the measurements of channels neighbor to a triggered one, even if belonging to a neighbor chip.
There are three ADCs per channel, characterized by a domino architecture. The first 6-bit ADC offers low-resolution analog-to-digital (A/D) conversion of the peak amplitude in a conversion time of about 25 ns. The serialized 6-bit data is available for each channel at a dedicated output after an event flag. Alternatively, the dedicated output provides one of four timing signals: time-over-threshold (ToT), threshold-to-peak (TtP), peak-to-threshold (PtT), or a 10 ns pulse occurring at peak (PtP). The second 10-bit ADC provides a higher resolution A/D con-version of the peak amplitude in a conversion time of about 200 ns from the occurrence of the peak. The third 8-bit ADC provides the A/D conversion of the peak timing, measured using a ramp-based time-to-amplitude converter (TAC) from the time of the peak to a stop signal. The TAC stop signal can be provided either externally or at a next count cycle of a shared 12-bit Gray-code counter which is incremented using an external clock. The counter value at the TAC stop is latched into a local 12-bit memory, thus providing a total of 20-bit deep timestamp with a nanosecond resolution. A total of 38 bits are associated with each event. The first bit is used as a flag for the readout of the event; the second is the threshold crossing indicator; a 6-bit word provides the channel address, followed by 10 bits associated with the peak amplitude, and 20 bits associated with the peak timing. The 38-bit data is stored in a 4-events deep FIFO and it is read out using a token passed first-come first-serve among the FIFOs that contain valid events.
The ASIC also provides at a dedicated output the address of the first above-threshold event (ART). Either at threshold crossing or at peak a flag is released followed by the serialized address. Additional functions include global and acquisition resets, pulse generator connected to the injection capacitor of each channel, a temperature sensor, analog monitor.
