22–26 Sept 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Development of Scalable Electronics for the TORCH Time-of-Flight Detector

24 Sept 2014, 11:10
25m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100

Speaker

Rui Gao (University of Oxford (GB))

Description

The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. It combines Time-Of-Flight and Cherenkov techniques to achieve particle separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons. Existing electronics has already demonstrated a 26ps intrinsic timing resolution, however the channel density needs improvements for future Micro Channel Plate (MCP) devices. This paper will report on a scalable design using custom ASICs (NINO-32 and HPTDC). The system provides up to 8x64 channels for a signal MCP device.

Summary

The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. In this detector, Time-Of-Flight and Cherenkov techniques are combined to achieve π/K/p separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons.
To read out a single 512-channel MCP, a typical electronics module consists of four NINO-32 boards, four HPTDC boards and a readout/ control board. Each NINO-32 board is equipped with two 32-channel fast amplifiers/ Time-Over-Threshold (TOT) NINO-32 ASICs, and a HPTDC board has two Time to Digital Convertor ASICs (HPTDCs) with a Spartan 3AN FPGA. NINO-32 ICs amplify the output signals from an MCP and measure the TOT of the pulse. Subsequently, the HPTDCs measure the time of the leading and trailing edges with respect to a trigger. The threshold of a NINO-32 is independently controlled by a DAC that can be set through the control board via an SPI port. The HPTDCs are intended to run in High Resolution Mode, which provides a 34ps RMS resolution with calibrations to maximize the channel density yet providing an adequate timing resolution (less than 70ps). In this way, the combination of one NINO32 and one HPTDC board can measure 64 channels. Alternatively, a Very High Resolution Mode is available on the HPTDC board to increase timing resolution to 17ps. However, the latter configuration reduces the number of channels by a factor of 4. The HPTDCs are read out and throttled by an FPGA. The outputs are buffered on the FPGA and then transferred to a computer via the readout system. The read out/ control board uses Giga-bit Ethernet and raw MAC protocol for data and control command transfer in both ways . This board also fans out clock and trigger signals to all HPTDCs in the module using low-jitter devices. In addition, general-purpose I/Os are available on the control board for integration with external systems, e.g. beam telescopes, test equipment, etc.
In addition to our existing GUI control software which provides basic data acquisition, configuration and monitoring, a command-line-based software package has also been developed. It incorporates a number of equipment drivers to allow automated scan of parameters, e.g. test-pulse width, NINO threshold, etc. The complete MCP readout system and its performance will be summarized.

This system is also designed to incorporate a charge-sharing measurement for future customized MCP devices. For instance, with a 8x64 channel MCP, this would resulting a 8x128 channel granularity, which fit the requirement of TORCH.

Author

Rui Gao (University of Oxford (GB))

Co-authors

Carmelo D'Ambrosio (CERN) Christoph Frei (CERN) David Cussans (University of Bristol (GB)) Didier Piedigrossi (CERN) Euan Cowie (University of Glasgow) Johan Maria Fopma (University of Oxford (GB)) Lucia Castillo Garcia (Ecole Polytechnique Federale de Lausanne (CH)) Maarten Van Dijk (University of Bristol (GB)) Prof. Neville Harnew (University of Oxford (GB)) Nicholas BROOK (BRISTOL) Roger Forty (CERN) Thierry Gys (CERN) Tibor Keri (University of Oxford (GB))

Presentation materials