Conveners
Trigger: B4b
- Wesley Smith (University of Wisconsin (US))
Trigger: B5a
- Stefano Veneziano (Universita e INFN, Roma I (IT))
Kristof Schmieden
(CERN)
24/09/2014, 14:50
Trigger
Oral
This talk focuses on the upgrades of the ATLAS central trigger processor (CTP) during the past year.
The increased energy and luminosity of the LHC in the next run period requires a more selective trigger menu in order to satisfy the physics goals of ATLAS.
Therefore the electronics of the CTP is upgraded and the commissioning status will be presented. In addition, the CTP software has been...
Yasuyuki Okumura
(University of Chicago (US))
24/09/2014, 15:15
Trigger
Oral
The first stage of the ATLAS Fast TracKer (FTK) is an ATCA-based input interface system, where hits from the entire silicon tracker must be clustered and organized into overlapping eta-phi trigger towers before being sent to the tracking processors. First, FTK Input Mezzanine cards receive hit data and perform clustering to reduce data volume. Then, the ATCA-based Data Formatter system will...
Nicola De Simone
(Universita e INFN Roma Tor Vergata (IT))
24/09/2014, 15:40
Trigger
Oral
The setup of the experiment NA62, studying ultra-rare decays of
charged kaons at the CERN SPS, is going to be completed for the first
physics data taking in the autumn of 2014. We present the final design,
implementation and the first on-field performance tests of the Level-0
trigger system of the Liquid Krypton calorimeter, photon veto in the
1-10 mrad region. The system is composed of...
Jim Hoff
(Fermilab)
25/09/2014, 09:50
Trigger
Oral
The VIPRAM approach has, from the beginning, attempted to increase pattern density and decrease power density through Vertical Integration. To mitigate issues implicit in adopting an emerging technology, a flexible architecture has been developed that can be implemented in either conventional or Vertically Integrated VLSI. This allows us to bring the system interface to maturity at an early...
Jamieson Olsen
(Fermilab)
25/09/2014, 10:15
Trigger
Oral
The Pulsar II is an FPGA-based full mesh ATCA processor board capable of creating a scalable architecture abundant in flexible, high bandwidth interconnections. The resulting full mesh interconnection among FPGAs is a natural fit for spatial and time multiplexed data processing. The design has been motivated by silicon-based tracking trigger needs for the LHC experiments. Near term...
