10th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Xi'an, China

Development of a low-noise, area efficiency, 4-order readout circuit for silicon pixel detectors

26 Sept 2015, 19:28

1m

Multi-function Hall (International Conference Center (Nanyang Hotel))

POSTER Pixels (incl. CCD's) - X-ray imaging After dinner POSTER session, with drinks: (All presenters are requested/encouraged to attend their posters; All participants are requested to participate the session, with drinks!)

Speaker

Dr JIA WANG (Northwestern Polytechnical University)

Description

In recent years, silicon detectors are widely used in X ray imaging for medical and astronomical applications. The signal induced by some particles is so weak that specified readout circuit is required. The readout circuit can be connected with silicon detectors by AC-coupling or DC-coupling method. DC-coupling is prefered for pixel detectors, since the AC-coupling capacitors required occupy much space and increase the complexity of the system, especially for large pixel array. However, the leakage current from the silicon crystal can be integrated on the feedback capacitor in charge sensitive amplifier (CSA). After a period, the operation point of the amplifier can be changed and it can not work well. Thus, the leakage current must be considered in the readout circuit design. Moreover, the area of one channel is limited by the system specification. This work will present an ASIC readout circuit development, which aims to achieving low noise and area efficiency. In order to compensate the leakage current, a dual CSA has been designed based on the previous works. The gain is increased. Pole-zero cancellation is also implemented to eliminate the overshoot/undershoot appearing in the output of shaper. A 4-order shaper is designed to obtain a Semi-Gaussian wave and further decrease the noise deduced by the leakage current. This circuit has been design and fabricated in a standard commercial 2P4M 0.35 $\mu m$ CMOS process. Die area of one channel is $1190 \mu m \times 147 \mu m$. The input charge range is 3 fC. The peaking time can be adapted from 1 us to 3 us. Measured ENC is about $70 e^-$ at input capacitor of 0 F. The gain is 180 mV/fC at the peaking time of 1 $\mu s$. The circuit is still under test. More measured results will be presented in this symposium.