10th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Xi'an, China

Soft Error Evaluation and Vulnerability Analysis in Xilinx Zynq-7010 System-on Chip System

26 Sept 2015, 19:51

1m

Multi-function Hall (International Conference Center (Nanyang Hotel))

POSTER Applications in Space, Medical, Biology, Material Sciences After dinner POSTER session, with drinks: (All presenters are requested/encouraged to attend their posters; All participants are requested to participate the session, with drinks!)

Speaker

Xuecheng Du (Xi’an Jiaotong University)

Description

Radiation-induced soft errors are an increasingly important threat to the reliability of modern electronic systems. The System-on Chip (SoC) includes a variety of electronic components, such as CPU and SRAM. Therefore, the dependability of SoC is becoming a serious issue in operating condition. In this work, we performed the single event effect testing in Xilinx Zynq-7010 SoC chip using 241Am alpha radiation source. The Programmable Logic (PL) , Direct Memory Access (DMA), Arithmetic Logical Unit (ALU), Float Point Unit (FPU), Quad-Flash controller, D-Cache and Registers were tested and the SoC failure modes were classified the Data errors , SEFI, Time-out and System halts. The device cross sections for different components and failures in time (FIT) were calculated. Based on fault tree analysis (FTA) approach, we established fault tree and calculated the SoC failure rate in Xilinx Zynq-7010 SoC using the Isograph Reliability Workbench 11.0. The method of qualitative analysis was used to determine the unique combinations of component failures that can cause system failure and the minimal cut sets. Moreover, the risk priority numbers of different components and the risk priority numbers of different failure modes were calculated using failure mode and effects analysis (FMEA) method. The risk priority number of PL was greater than other components based on the calculated results. The results illustrated the PL was the most sensitive part of Xilinx Zynq-7010 SoC and the Quad-Flash controller was the last. The data of risk priority number of different failure modes inferred that data errors was the most crucial failure mode in Zynq-7010 SoC and the Time-out event was least failure. Throughout the above FTA and FEMA approaches, we identified the critical components and major failure modes. The vulnerability in Xilinx Zynq-7010 SoC was clearly analyzed.