65 nm CMOS analog front-end for pixel detectors at the HL-LHC (in session "ASICs")
65k pixel X-Ray camera module of 75µm pixel size (in session "Poster")
A 12-bit 60-MS/s 36-mW SHA-less Opamp-Sharing Pipeline ADC in 130nm CMOS (in session "Poster")
A 12b Rad-Hard Digital Calibrated Single Slope ADC for LHC environment (in session "Poster")
A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout (in session "Poster")
A 128-channel event driven readout ASIC for the R3B Tracker (in session "ASICs")
A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS Driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip. (in session "Poster")
A fast multichannel, ultra-low power 10-bit ADC for readout of future particle physics detectors (in session "ASICs")
A Fast Turn-on ADC Scheme and its Engineering Validation (in session "Poster")
A framework for porting the NeuroBayes machine learning algorithm to FPGAs (in session "Programmable Logic, design tools and methods")
A front-end ASIC for ionising radiation monitoring with femto-amp capabilities (in session "Poster")
A High Bandwidth and versatile Advanced MC Board (in session "Poster")
A High Frame Rate Pixel Chip Design for Synchrotron Radiation Applications (in session "ASICs")
A low jitter PLL frequency synthesizer for high resolution TDCs in 65nm CMOS technology (in session "ASICs")
A multi-Gigabyte per Second PCI-Express Data Link for Real-Time DAQ Systems (in session "Poster")
A new approach to front-end electronics interfacing in the ATLAS experiment (in session "Systems, Planning, installation, commissioning and running experience")
A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform (in session "Systems, Planning, installation, commissioning and running experience")
A New Way to Implement High Performance Pattern Recognition Associative Memory in Modern FPGAs (in session "Poster")
A Novel Approach for Pulse Width Measurements in an FPGA (in session "Programmable Logic, design tools and methods")
A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade (in session "Poster")
A radiation tolerant Data link board for the ATLAS TileCal upgrade (in session "Radiation tolerant components and systems")
A Signal Distribution Board for the Timing and Fast Control Master of the CBM Experiment (in session "Poster")
A Silicon Photonic Wavelength Division Multiplex System for High-Speed Data Transmission in Detector Instrumentation (in session "Poster")
A time-based front-end ASIC for the Silicon micro-strip sensors of the PANDA Micro Vertex Detector (in session "Poster")
Algorithm and implementation of muon trigger and data transmission system for barrel-endcap overlap region of the CMS detector (in session "Poster")
Alice CTP upgrade (in session "Trigger")
ATLAS Pixel Detector ROD card from IBL towards Layers 2 and 1 (in session "Production, testing and reliability")
ATLAS Transition Radiation Tracker (TRT) Electronics Operation Experience at High Rates (in session "Poster")
Board-mount miniature optical transmitters and transceivers for detector readout in particle physics experiments (in session "Poster")
Characterization of a Three-Side Abutable Cmos Pixel Sensor with Digital Pixel and Data Compression for Charged Particle Tracking : PIXAM (in session "Poster")
Charge Collection Properties of a Depleted Monolithic Active Pixel Sensor using a HV-SOI process (in session "ASICs")
Close out (in session "Close out")
CMS DT Upgrade: The Sector Collector Relocation (in session "Systems, Planning, installation, commissioning and running experience")
Commissioning of the on-detector electronics of a novel GEM-based detector for the CMS experiment (in session "Poster")
Commissioning of the Upgraded CSC Endcap Muon Port Cards at CMS (in session "Poster")
Common Readout Unit (CRU) – A new readout architecture for ALICE experiment (in session "Systems, Planning, installation, commissioning and running experience")
Comparison of two fast, ultra-low power 10-bit SAR ADCs in CMOS 130 nm A and B technologies (in session "Poster")
Construction and Test of the First Belle II SVD Ladder Implementing the Origami Chip-on-Sensor Design (in session "Packaging and interconnects")
Construction, Testing, Installation, Commissioning and Operation of the CMS Calorimeter Trigger Layer-1 CTP7 Cards (in session "Poster")
COTS ADC for the Accelerator Radiation Environment (in session "Poster")
DARE platforms: Past, present, future (in session "Plenary")
Deployment of the CTA AMC as Backend for the CMS Pixel Detector (in session "Systems, Planning, installation, commissioning and running experience")
Design and Electronics of the CBM Micro-Vertex-Detector (in session "Poster")
Design and results of a 65 nm digital readout Macro Pixel ASIC (MPA) prototype with on-chip particle recognition for the Phase II CMS Outer Tracker upgrade (in session "ASICs")
Design of a 10-bit segmented current-steering Digital-to-Analog Converter in CMOS 65nm technology for the bias of new generation readout chips in high radiation environment (in session "Poster")
Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector (in session "Poster")
Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger (in session "Trigger")
Design of Si-Photonic structures and evaluation of their radiation hardness dependence on design parameters (in session "Poster")
Design of the NSW Read Out Controller ASIC (in session "Poster")
Detector Developments at DESY for Free-Electron Lasers (in session "Invited Plenary")
Development and experimental study of the Read-out ASIC for Muon Chambers of the CBM Experiment (in session "Poster")
Development and performance studies of TORCH readout electronics using custom MCPs in a test-beam (in session "Poster")
Development of a low power Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) in 130nm CMOS technology (in session "ASICs")
Development of a Radiation-Tolerant Component for the Quench Protection System (in session "Poster")
Development of a Standardized Readout System for Active Pixel Sensors in HV/HR-CMOS Technologies for ATLAS Inner Detector Upgrades (in session "Poster")
Development of a sub-nanosecond time-to-digital converter based on field-programmable gate array (in session "Poster")
Development of ATLAS Liquid Argon Calorimeter Read-out Electronics for the HL-LHC (in session "Radiation tolerant components and systems")
Development of the 40 MHz readout for the upgraded LHCb VELO (in session "Poster")
Development on CMOS MAPS devices for the ATLAS Phase-II Strip Tracker Upgrade (in session "ASICs")
EMC Studies for the Vertex Detector of the Belle II Experiment (in session "Power, Grounding and Shielding")
ESA Microelectronic Developments for space (in session "Invited Plenary")
Europractice EDA tools for the HEP community: 2015 update (in session "Microelectronics User Group")
Evaluation of a commercial AdvancedTCA board management controller solution (in session "Poster")
Experience from design, prototyping and production of a DC-DC conversion powering scheme for the CMS Phase-1 Pixel Upgrade (in session "Poster")
FATALIC: A dedicated Front-End ASIC for the Atlas TileCal Upgrade (in session "ASICs")
FE65_P2: Prototype Pixel Readout Chip in 65nm for HL-LHC Upgrades (in session "Poster")
First large volume characterization of the QIE10/11 custom front-end integrated circuits (in session "Poster")
First Performance Results of the ALICE TPC RCU2 (in session "Systems, Planning, installation, commissioning and running experience")
FPGA implementation of PCI-express bifurcation for high-throughput data acquisition (in session "Poster")
Front End ASIC for AGIPD, a high dynamic range fast detector for the European XFEL (in session "ASICs")
Front End Electronics for SiPM Readout in the Mu2e CRV Detector (in session "Systems, Planning, installation, commissioning and running experience")
Front end Optimization for the Monolithic Active Pixel Sensor of the ALICE Inner Tracking System Upgrade (in session "ASICs")
Front-end electronics for Micro Pattern Gas Detectors with integrated input protection against discharges (in session "Poster")
Front-End electronics for the FAZIA project (in session "Poster")
GBLD10+: A Compact Low-power 10 Gb/s VCSEL Driver IC (in session "ASICs")
GBT Link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards (in session "Poster")
GEMMA and GEMINI, two dedicated mixed-signal ASICs for Triple-GEM detectors readout (in session "Poster")
Genesis of a Workshop (in session "Opening")
Hardware evaluation of Xilinx High Level Synthesis for building data readout systems – a CMS ECAL Data Concentrator Card case (in session "Poster")
High dynamic range diamond detector acquisition system for beam wire scanner applications (in session "Poster")
High resolution timing detectors and electronics: an overview (in session "Invited Plenary")
High Speed Data Transmission on Small Gauge Cables for the ATLAS Pixel Upgrade (in session "Poster")
High speed readout solution for single-pixel-photon counting ASICs (in session "Poster")
High-energy physics and associated technologies in Portugal (in session "Opening")
High-Performance Analog-to-Digital Converters - Evolution and Trends (in session "Opening")
Implementation of the Timepix chip in the Scalable Readout System (in session "Programmable Logic, design tools and methods")
Instrument Readout for the European Spallation Source (in session "Poster")
ITER Electronics (in session "Opening")
KLauS: A low power Silicon Photomultiplier Charge Readout ASIC in .18 UMC CMOS (in session "ASICs")
LHCb RICH Upgrade: an overview on the photon detector and the electronics system. (in session "Poster")
Library Characterization Techniques for 65nm and 130nm Technologies (in session "Microelectronics User Group")
LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps serializer ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade (in session "Poster")
Low Voltage Power for the ATLAS New Small Wheel Muon Detector (in session "Poster")
Low-Cost Bump-Bonding Process for High Energy Physics Pixel Detectors (in session "Poster")
MicroTCA and AdvancedTCA equipment evaluation and developments for LHC experiments (in session "Systems, Planning, installation, commissioning and running experience")
Multi-Gigabit Wireless Data Transfer using the Millimeter Wave Band at 60 GHz (in session "Poster")
NaNet-10: a 10GbE Network Interface Card for the GPU-based Low-Level Trigger of the NA62 RICH Detector. (in session "Poster")
New Fast Beam Conditions Monitoring (BCM1F) system for CMS. (in session "Poster")
News on Foundry Services (in session "Microelectronics User Group")
Ongoing studies for the control system of a serially powered ATLAS pixel detector at the HL-LHC (in session "Poster")
Open Discussion (in session "Microelectronics User Group")
Opening (in session "Opening")
Opening Local Organizer (in session "Opening")
Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of Run-2 (in session "Plenary")
Operation of the upgraded ATLAS Level-1 Central Trigger System (in session "Trigger")
Overview and Future Developments of the FPGA-based DAQ of COMPASS (in session "Systems, Planning, installation, commissioning and running experience")
PACIFIC: The readout ASIC for the SciFi Tracker planned for the upgrade of the LHCb detector (in session "ASICs")
Past and future microelectronics in HEP (in session "Invited Plenary")
Performance of the Demonstrator System for the Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid-Argon Calorimeters (in session "Systems, Planning, installation, commissioning and running experience")
Performance of the new Amplifier-Shaper-Discriminator chip for the ATLAS MDT Chambers at the HL-LHC (in session "Poster")
Performance of the prototype readout system for the CMS endcap hadron calorimeter upgrade (in session "Poster")
Performance of the sROD demonstrator for the ATLAS Tile Calorimeter Phase II Upgrade (in session "Poster")
Performances of a Remote High Voltage Power Supply for the Phase II Upgrade of the ATLAS Tile Calorimeter (in session "Poster")
Performances of the EUSO-Balloon electronics (in session "Systems, Planning, installation, commissioning and running experience")
Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments (in session "Poster")
Polyurethane spray coating of aluminum wire bonds to prevent corrosion and suppress resonant oscillations (in session "Poster")
Power Distribution for the ATLAS LAr Trigger Digitizer Board (in session "Poster")
Preparing the hardware of the CMS Electromagnetic Calorimeter control and safety systems for LHC Run 2 (in session "Poster")
Processing of the Liquid Xenon Calorimeter’s signals for timing measurements. (in session "Poster")
Prototype active silicon sensor in LFoundry 150nm HV/HR-CMOS technology for ATLAS Inner Detector Upgrade (in session "ASICs")
Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade (in session "ASICs")
Pulsar IIb Design, System Integration and Next-Generation Full Mesh ATCA Backplane Test Results (in session "Poster")
QIE12: A New High-Performance ASIC For the ATLAS TileCal Upgrade (in session "Poster")
Qualification of the CMS Phase 1 Upgrade HF Front-end Electronics (in session "Systems, Planning, installation, commissioning and running experience")
Rad-Hard Vertical JFET switch for the HV-MUX system of the ATLAS upgrade ITk (in session "Poster")
Radiation hard Regulator circuits for the ALICE ITS Upgrade (in session "Poster")
Radiation tolerance of the readout chip for the Phase I upgrade of the CMS pixel detector (in session "Radiation tolerant components and systems")
Readout and data acquisition in the NEW detector based on SRS-ATCA (in session "Poster")
Redundant SAR ADC architecture and circuit techniques for ATLAS LAr Phase-II upgrade (in session "ASICs")
Results from longevity studies of the on-detector readout of the CMS Electromagnetic calorimeter (in session "Poster")
SALT, a dedicated readout chip for strip detectors in the LHCb Upgrade experiment (in session "Poster")
SAMPA Chip: a New ASIC for the ALICE TPC and MCH Upgrades (in session "ASICs")
Self-Triggering Readout System for the Neutron Lifetime Experiment PENeLOPE (in session "Poster")
SEU Mitigation Techniques for SRAM based FPGAs (in session "Invited Plenary")
Simulation of Digital Pixel Readout Chip Architectures for the LHC Phase 2 Upgrades with a SystemVerilog-UVM Verification Environment (in session "Poster")
Standardization of automated industrial test equipment for mass production of control systems (in session "Poster")
Status and Future Prospects of High Time Resolution Photon Counting Sensor Arrays (in session "Invited Plenary")
Status Of The Central Logic Board Of The KM3NeT Neutrino Telescope (in session "Poster")
Test of a demonstrator of an MDT-based first level muon trigger for HL-LHC under realistic operating conditions. (in session "Poster")
The ALICE HLT Readout Upgrade for Run2 (in session "Poster")
The Clock and Control System for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade (in session "Poster")
The CMS Beam Halo Monitor Electronics (in session "Poster")
The CMS Level-1 Trigger Barrel Track Finder (in session "Poster")
The CMS TCDS Installation (in session "Systems, Planning, installation, commissioning and running experience")
The Evolution of the Region of Interest Builder in the ATLAS experiment (in session "Poster")
The Giga Bit Transceiver based Expandable Front-End (GEFE) - a new radiation tolerant acquisition system for beam instrumentation (in session "Poster")
The Level-0 Trigger of the NA62 Liquid Krypton Calorimeter and its performance during first data-taking activities in 2015. (in session "Poster")
The Level-0 Trigger Processor for the NA62 experiment (in session "Poster")
The NA62 Liquid Krypton calorimeter readout system. (in session "Poster")
The NA62 spectrometer acquisition system (in session "Systems, Planning, installation, commissioning and running experience")
The New Front-End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade (in session "Poster")
The PCIe-based readout system for the LHCb experiment (in session "Systems, Planning, installation, commissioning and running experience")
The Phase-1 Upgrade of the ATLAS First Level Calorimeter Trigger (in session "Trigger")
The readout electronics of the SciFi Tracker for LHCb detector upgrade (in session "Systems, Planning, installation, commissioning and running experience")
The SST-1m prototype camera for the Cherenkov Telescope Array (in session "Poster")
The STAR Heavy Flavor Tracker PXL detector readout electronics (in session "Systems, Planning, installation, commissioning and running experience")
The upgrade of the CMS Global Trigger (in session "Poster")
TID Effects in 65nm Transistors: Summary of a Long Irradiation Study at the CERN X-rays Facility (in session "Microelectronics User Group")
TOFPETv2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications (in session "Poster")
TopMetal2-: a direct charge-collecting sensor for high energy physics and imaging in XFAB 350nm process (in session "Poster")
Towards a 65nm Pixel Readout Chip for ATLAS and CMS High Luminosity Upgrades (in session "Plenary")
Track Finding in CMS for the Level-1 Trigger at the HL-LHC (in session "Trigger")
Transmission Lines Implementation on HDI Flex Circuits for the CMS Tracker Upgrade (in session "Poster")
Trigger Algorithms and electronics for the ATLAS Muon NSW Upgrade (in session "Trigger")
Trigger and readout electronics for the STEREO experiment. (in session "Poster")
Trigger architecture of the SuperNEMO experiment (in session "Trigger")
Triggering on electron, jets and tau leptons with the CMS upgraded calorimeter trigger for the LHC RUN II (in session "Poster")
Upgrade of the ALICE Silicon Tracker Using CMOS Pixel Sensors (in session "Invited Plenary")
Upgrade of the ALICE TPC FEE online radiation monitoring system (in session "Poster")
Upgrades to the CMS Level-1 calorimeter trigger (in session "Plenary")
Versatile prototyping platform for Data Processing Boards for CBM experiment (in session "Poster")
Welcome from Professor Rogério Colaço (in session "Opening")
Include materials from selected contributions
