28 September 2015 to 2 October 2015
Lisbon
Europe/Zurich timezone

The PCIe-based readout system for the LHCb experiment

1 Oct 2015, 16:30
25m
Sala 02.1 (Lisbon)

Sala 02.1

Lisbon

IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal

Speaker

Frederic Rethore (Centre National de la Recherche Scientifique (FR))

Description

The upgrade of the LHCb experiment at CERN will implement a trigger-less readout system in which all the data are transported to the computing farm over 12000 optical links without hardware filtering. The event building and event selection is entirely operated in the farm. Another originality of the system is that data from the detector arrive directly in computers through a specially designed PCIe card called PCIe40. This presentation will explain these design choices and will describe the performance of the PCIe40 board and the overall system.

Summary

The LHCb experiment is designed to study differences between particles and anti-particles as well as very rare decays in the beauty and charm sector at the LHC. However, the existing hardware trigger running at maximum 1 MHz introduces limits in LHCb’s data-taking capabilities.
Therefore, the detector will be upgraded in 2018 in order to significantly increase its efficiency. It will implement a trigger-less readout system in which all the data from every LHC bunch-crossing are transported to the computing farm over 12000 optical links without hardware filtering. The event building and event selection are carried out entirely in the farm.
Another original feature of the system is that data transmitted through these fibres arrive directly in computers through a specially designed PCIe card called PCIe40.

The same board handles the data acquisition flow and the distribution of fast and slow controls to the detector front-end electronics. It embeds one of the most powerful FPGAs currently available on the market with 1.2 million logic cells. The board has a bandwidth of 480 Gbits/s in both input and output over optical links and 100 Gbits/s in each direction over the PCI Express bus to the CPU.

We will present how data circulate through the board and in the PC server for achieving the event building.

We will focus on specific issues regarding the design of such a board with a very large FPGA, in particular in terms of power supply dimensioning and thermal simulations.

The features of the board will be detailed and we will finally present the first performance measurements.

Primary author

Frederic Rethore (Centre National de la Recherche Scientifique (FR))

Co-authors

Frederic Hachon (Centre National de la Recherche Scientifique (FR)) Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR)) Renaud Le Gac (CPPM CNRS/IN2P3)

Presentation Materials