During the LHC shutdown in 2018/19 and as a part of the LHCb upgrade, the Tracking Stations downstream from the magnet will undergo a detector technology change. A new tracker, built of 2.5m long and 250µm thick scintillating fibres sensed with silicon photomultipliers (SiPMs), will be installed to cope with the increased hit occupancy and radiation environment, allowing to increase the readout rate to 40MHz.
The low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC) grants the 40MHz readout of the scintillating fibers without deadtime. It will connect directly to the anode of the SiPMs, performing the sensor conditioning, analog processing and digitization of 64 channels. The power budget was limited to 8mW/channel. The 130nm CMOS process was chosen for its wide use in radiation-tolerant applications. Two prototypes were produced in IBM technology and a third will be submitted shortly to TSMC, allowing to present simulation and test results.
The input stage is a current mode amplifier composed of a current conveyor and a closed-loop transimpedance amplifier. The current conveyor is based on a novel double feedback approach and optimized for SiPM arrays with anode connections. The double loop provides independent control over the anode voltage and the input impedance over the full bandwidth (>250MHz). This stage has a low power consumption (<2mW) and a selectable gain that assures a good single cell resolution for calibration.
The signal received by the ASIC extends over several LHC clock cycles, mainly due to the recovery of the SiPM. Additionally, the distribution of the time of arrival of the scintillation light spreads over 60% of the LHC clock cycle. The goal of the shaping stage is to reduce the pulse width to allow a 10ns integration, thus minimizing spillover and the effect of the signal arrival time on pulse height measurement. A tunable double pole-zero shaper allows to independently cancel the longer exponential decay related to different SiPM capacitances and quenching resistors, as well as the shorter time component, associated with parasitic capacitance and the amplifier input impedance. It is a closed-loop design based on an OTA with high gain-bandwidth product (>300MHz), low power consumption (<700µW), and high load-driving capability, for a fast rising edge. The output offset is controlled using an additional baseline restoration feedback loop.
The pulse is accumulated with a gated integrator based on an amplifier with sufficient gain-bandwidth product (>150MHz), low power consumption (<400µW), and high slew-rate (>100V/µs). The integration time was set close to the full clock period to cope with the dispersion of the signal time of arrival, so two integrators had to be interleaved to allow time for reset.
The integrator outputs are independently sampled with interleaved active miller track and hold circuits based on the same OTA used in the shaper. Three hysteresis comparators with tunable references complete the 2bit nonlinear flash ADC operating at 40MHz. Finally, a serializer generates a 160MSa/s stream from the data of two channels.