September 28, 2015 to October 2, 2015
Lisbon
Europe/Zurich timezone

Triggering on electron, jets and tau leptons with the CMS upgraded calorimeter trigger for the LHC RUN II

Sep 30, 2015, 5:32 PM
1m
Hall of Civil Engineering (Lisbon)

Hall of Civil Engineering

Lisbon

IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal
Poster Poster

Speaker

Alexandre Zabi (Centre National de la Recherche Scientifique (FR))

Description

The design of the upgraded CMS Level-1 calorimeter trigger is based on a novel concept the Time Multiplexed Trigger (TMT). In this design there are nine main processing nodes each of which receives the data from an entire event. The nine processing nodes are fed data from a TMT switch which consists of 36 processors whose job is to collect fragments of events from each bunch crossing and construct entire events. This design is not different from that of the CMS DAQ and HLT systems. The advantage of this design is that there is no data sharing between the processing nodes each of which receives all the data from one event at high granularity and dynamic range. This opens up the possibility of designing highly sophisticated algorithms for the Level-1 trigger whose efficiency approaches the efficiency of the HLT algorithms. The details of the firmware and software design as well as the performance of the Level-1 trigger algorithms for the 2016 LHC run are presented in this poster.

Summary

This poster will present the design and the implementation of the firmware algorithms performing the electrons, photons, jets and tau leptons selection at the Level-1 CMS calorimeter trigger for the run II of the LHC. This new system is planned to be replacing the existing level-1 calorimeter trigger starting 2016. As the LHC restarts and delivers higher luminosity collisions, exceeding the design parameters, the current CMS trigger system will not be capable of maintaining the high efficiency required for the CMS physics program. The replacement of the trigger system is also a good opportunity to consider even more efficient ways of selecting electrons, photons, tau leptons, reconstructing jets and performing energy sums. In these intense conditions, the implementation of pile-up mitigation techniques is required to reach acceptable performance.

Modern technologies offer an effective solution to achieve these goals. The 2016 system being commissioned to run in parallel starting this fall will be based on the microTCA electronics standard. The innovative approach of the Time Multiplexed Trigger (TMT), which will be presented on the poster, allows to perform physics objects selections and pile-up mitigation in an optimized way.

The trigger primitives generated by the detector will be transmitted by newly installed optical link boards (4.5 to 6.4 Gb/s) replacing the existing copper cables (1.2 Gb/s), to the new microTCA crates. The system is based on custom designed AMC (Advanced Mezzanine Boards) with Xilinx Virtex 7 FPGAs. These boards provide up to 144 high-speed optical serial links, running at speeds up to 10 Gbps allowing to gather information from the entire calorimeter for each event in one FPGA, where sophisticated algorithms may be implemented. The complete view of the calorimeter will allow the trigger to compute global quantities such as the average energy density that can be used to estimate the pile-up level. The resulting increase in rejection power will permit the experiment keep low trigger thresholds on physics objects.

The firmware design benefits from an optimized approach to perform sums to build jet candidates and dynamic clustering to reconstruct the electron footprint. Tau leptons are built from basic clusters to improve the efficiency on all possible decay modes. Adapted calibration techniques are used to improve on the response and the enhanced granularity available allows to achieve excellent angular resolutions for these objects. The poster will present the details of the firmware algorithms and their performance that are beyond expectations for a Level-1 hardware based system. Particular emphasis is placed on the results from the undergoing final commissioning tests directly on the system.

Primary author

Alexandre Zabi (Centre National de la Recherche Scientifique (FR))

Presentation materials