Conveners
Poster: Session 1
- Ken Wyllie (CERN)
- Mitchell Franck Newcomer (University of Pennsylvania (US))
Poster: Session 2
- Ken Wyllie (CERN)
- Mitchell Franck Newcomer (University of Pennsylvania (US))
Mr
Chaosong Gao
(Central China Normal University CCNU (CN))
9/29/15, 4:30 PM
ASICs
Poster
This work presents the design and characterization of TopMetal2- chip, a direct charge-collecting sensor via 25x25um2 top metal placed on the top of each pixel. The TopMetal2- chip has been manufactured in the XFAB 350nm CMOS Imaging Sensor process. The TopMetal2- features 72x72 pixel array of 83.2um pixel pitch. Post-layout simulations and test results show the gain of charge sensitive...
Alessandro Pezzotta
(University of Milano-Bicocca)
9/29/15, 4:31 PM
ASICs
Poster
GEMMA and GEMINI, two integrated frontends for the Triple-GEM detector are presented. The ASICs aim to improve detector readout performance in terms of count rate, adaptability, portability and power consumption. GEMMA target is to embed counting, timing and spectroscopic measurements in a single 8-channel device, managing a detector capacitance up to 15pF. GEMINI is dedicated to counting...
Flavio Loddo
(INFN-BARI)
9/29/15, 4:33 PM
ASICs
Poster
A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good...
Agostino Di Francesco
(LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
9/29/15, 4:34 PM
ASICs
Poster
We present the design and simulation of a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit, designed in standard CMOS 110 nm technology, has 64 independent channels optimized for time-of-flight measurement in PET or other applications. The chip has quad-buffered TDCs and charge integration ADCs in each channel with linear response in the range...
mohamed zeloufi
(LPSC)
9/29/15, 4:35 PM
ASICs
Poster
We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. The total of capacitors used in this architecture is limited to a half of the one in a classical SAR...
Susanne Kersten
(Bergische Universitaet Wuppertal (DE))
9/29/15, 4:36 PM
ASICs
Poster
In terms of the Phase-2 Upgrade of the ATLAS detector, the entire inner tracker (ITK) of ATLAS will be replaced. This includes the pixel detector and the corresponding detector control system (DCS). The current baseline is a serial powering scheme of the detector modules. Therefore a new detector control system for ATLAS pixel is being developed with emphasis on the supervision of serially...
Fabrice Guilloux
(CEA/IRFU - Centre de Saclay (FR))
9/29/15, 4:37 PM
ASICs
Poster
CMOS pixel sensor technology has been chosen to equip the new trackers in ALICE foreseen for HL-LHC. PIXAM is the final prototype from a R&D program specific to the Muon Forward Tracker which intends to push significantly forward the performances of the mature rolling shutter (RS) architecture. By implementing a digital pixel in addition with group of rows for the readout operation, the PIXAM...
Gary Drake
(Argonne National Laboratory (US))
9/29/15, 4:38 PM
ASICs
Poster
We present results on the QIE12, a custom ASIC, being developed for the ATLAS TileCal Phase 2 Upgrade. The design features 1.5 fC sensitivity, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. It has a programmable shunt output for monitoring the integrated current. The device operates with no dead-time at 40 MHz, making it...
Alessandra Lattuca
(Universita e INFN Torino (IT))
9/29/15, 4:39 PM
ASICs
Poster
This work presents two essential components for the high speed data transmission of the ALICE inner detector front-end chip. The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz clock for the 1.2 Gb/s Double Data Rate serializer and a 200 MHz output for the 400 Mb/s driver. The pseudo-LVDS driver transmits the data from the pixel chip with a limited number of signal lines....
Robert Richter
(Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
9/29/15, 4:40 PM
ASICs
Poster
The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for MDT drift tubes. The first processing stage, the channel Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed,...
Radu Mihai Coliban
9/29/15, 4:41 PM
ASICs
Poster
Part of the New Small Wheel ATLAS Phase-1 Upgrade, the Read Out Controller ASIC will aggregate, process and format the data generated by the VMM front-end chips. The ASIC has a flexible architecture designed to optimize the data bandwidth usage for Micromegas and sTGC detectors and for different NSW regions with different hit rates. The ROC will concentrate the Level-0 data streams from up to...
Mr
Valentino Di Pietro
(II. Physikalisches Institut, JLU Gießen)
9/29/15, 4:42 PM
ASICs
Poster
Among the many detectors planned for the PANDA experiment that will take place at the future FAIR accelerator facility, the innermost is the Micro Vertex Detector (MVD). This detector foresees both pixel and strip silicon sensors. The readout chip for the strip sensors of the MVD, named PASTA (PAnda STrip Asic), was developed according to a time-based architecture aiming at Time over Threshold...
Olivier Raymond Bourrion
(Centre National de la Recherche Scientifique (FR))
9/29/15, 4:53 PM
Systems
Poster
The STEREO experiment will search for a sterile neutrino by measuring the anti-neutrino energy spectrum as a function of the distance from the source, the ILL nuclear reactor.
A dedicated electronic, hosted in a single µTCA crate, was designed for this experiment. It performs triggering in two stages with various selectable conditions, processing and readout via UDP/IPBUS on 68...
Dr
Raul Esteve
(Universitat Politècnica de València)
9/29/15, 4:54 PM
Systems
Poster
The Scalable Readout System (SRS) was defined by the CERN RD51 Collaboration as an scalable readout platform for a wide range of front ends. In 2014, SRS was ported to the ATCA (Advanced Telecommunications Computing Architecture) standard.
NEXT is an underground experiment aimed at searching for neutrinoless double-beta decay. NEXT-DEMO, a small-scale demonstrator, was read-out using SRS....
Vladimir Ryjov
(CERN)
9/29/15, 4:55 PM
Systems
Poster
The NA62 experiment at CERN SPS accelerator will study the ultra-rare decays of charged kaons. The high-resolution Liquid Krypton (LKr) electromagnetic calorimeter is a key component of the experiment photon-veto system.
The new LKr readout system comprises 14 thousand 14-bit ADC acquisition channels, 432×1 Gbit Ethernet data request and readout links routed by 28×10 Gbit network switches to...
Manoel Barros Marin
(CERN)
9/29/15, 4:56 PM
Systems
Poster
The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multipurpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of...
Hans Kristian Soltveit
(University of Heidelberg)
9/29/15, 4:58 PM
Systems
Poster
Wireless techniques have developed extremely fast the last decade, and using them for data transfer in particle phyics detectors is not science fiction any more. In this paper we describe the status of the first prototype of the 60 GHz wireless Multi-Gigabit data transfer topology current under development at University of Heidelberg using IBM 130 nm SiGe HBT technology.
The wireless...
Julia Katharina Rieger
(Georg-August-Universitaet Goettingen (DE))
9/29/15, 5:02 PM
Systems
Poster
The LHC Phase-II Upgrade results in new challenges for tracking detectors in terms of cost effectiveness, resolution, etc. Active Pixel Sensors in HV/HR - CMOS technologies show promising results coping with these challenges. In order to demonstrate the feasibility of the hybrid modules of active CMOS sensor and readout chip for the future ATLAS Inner Tracker, an ATLAS R&D project has...
Franck SALOMON
(Institut de Physique Nucléaire d'Orsay)
9/29/15, 5:03 PM
Systems
Poster
FAZIA is a multidetector specifically designed to optimize ion identification in heavy-ion experiments. This multidetector is modular and it is based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI scintillator associated to a photodiode. Its electronic is fully digital. The objective to push at maximum the ion identification capability while preserving...
Enrico Junior Schioppa
(Universite de Geneve (CH))
9/29/15, 5:04 PM
Systems
Poster
A prototype camera for the single mirror Small Size Telescope (SST-1m) of the Cherenkov Telescope Array has been designed and is under construction. The camera is a hexagonal matrix of 1296 large area (95 mm^2) hexagonal silicon photomultipliers. The fully digital readout and trigger system, DigiCam, allows for high data transfer rates in an extremely compact design. The camera will be...
Fernando Carrio Argos
(Instituto de Fisica Corpuscular (ES))
9/29/15, 5:05 PM
Systems
Poster
The super Read Out Driver (sROD) demonstrator is a high performance double AMC board based on FPGA resources and QSFP modules. This board has been designed in the framework of the ATLAS Tile Calorimeter (TileCal) Demonstrator Project for the Phase II Upgrade as the first stage of the off-detector electronics. The sROD demonstrator has been conceived for receiving and processing the data coming...
Tiankuan Liu
(Southern Methodist University)
9/29/15, 5:06 PM
Systems
Poster
A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to demonstrate the functionality of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system, which uses ASICs including GBTX and GBT SCA at the front end,...
Mr
Dominic Gaisbauer
(TU München Physikdepartment E18)
9/29/15, 5:07 PM
Systems
Poster
PENeLOPE is an a neutron lifetime measurement experiment at the Forschungsreaktor Muenchen II aiming to improve a precision of the measurement by one order of magnitude. The experiment employes state-of-the-art readout electronics and high performance data acquisition system.
The system features a continuos noise measurement and pedestal tracking, programmable threshold, high voltage...
Ms
Agnieszka Zagozdzinska
(CERN/WUT)
9/29/15, 5:08 PM
Systems
Poster
The CMS Beam Radiation Instrumentation and Luminosity (BRIL) project is composed of several systems providing the experiment protection from adverse beam conditions, measuring the online luminosity and beam background. Although the readout bandwidth of the Fast Beam Conditions Monitoring system (BCM1F), was sufficient for the initial LHC conditions, the foreseen enhancement of the beams...
Nicolo Tosi
(Universita e INFN, Bologna (IT))
9/29/15, 5:10 PM
Systems
Poster
The CMS Beam Halo Monitor was installed during LHC LS1 to measure the machine induced background for Run II.
The system is composed of Cherenkov radiators coupled to photomultipliers.
The readout electronics uses new components developed for the CMS HCAL, adapted to beam monitoring requirements.
The signal is digitized by a charge integrating ASIC (QIE10), which also provides timing with ns...
Agostinho Da Silva Gomes
(LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
9/29/15, 5:11 PM
Systems
Poster
The Tile Calorimeter (TileCal) is the main hadronic calorimeter of the ATLAS experiment. TileCal will undergo a major replacement of its readout electronics for the upgrade of the LHC in 2024. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. Three...
Lukas Meder
(Karlsruhe Institute of Technology)
9/29/15, 5:12 PM
Systems
Poster
For the CBM experiment a Timing and Fast-Control (TFC) system is being developed. In the detector readout, FPGA-based data processing boards (DPB) are organized in a large number of computing crates. At the crate level, the TFC master is connected to one TFC slave per crate, whereas the DPB AMCs are interconnected by the crates’ infrastructure. In this article, an FMC-based signal distribution...
Mr
Mikhail Matveev
(Rice University)
9/29/15, 5:23 PM
Trigger
Poster
We report on the status of commissioning of the upgraded Muon Port Cards in the Level 1 Trigger electronic system serving the Endcap Cathode Strip Chamber (CSC) sub-detector at the CMS experiment at CERN. After presenting an overview of the existing system and upgrade requirements, we describe the new Muon Port Card FPGA mezzanine and its firmware developed to drive the new 3.2Gbps...
Dario Soldi
(Universita e INFN Torino (IT))
9/29/15, 5:24 PM
Trigger
Poster
In the NA62 experiment at CERN-SPS, the communication between detectors and the Lowest Level (L0) trigger processor is performed via ethernet packets, using the UDP protocol. The L0 trigger processor handles the signals from sub-detectors that take part to the trigger generation and, in order to chose the best solution, two different approaches have been implemented.
The first approach is...
Hubert Kroha
(Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
9/29/15, 5:25 PM
Trigger
Poster
Selective triggers are essential for the programme of the ATLAS experiment at the HL-LHC. Its first level muon trigger rate is dominated by low momentum muons, selected due to the moderate resolution of the trigger chambers. This limitation can be overcome by including the precision muon drift tube (MDT) chamber data. This requires a fast MDT read-out and fast track reconstruction. A...
Giacomo Fedi
(Universita di Pisa & INFN (IT))
9/29/15, 5:26 PM
Trigger
Poster
The increase of luminosity at the High Luminosity Large Hadron
Collider (HL-LHC) will require the main experiments to use the tracker
information at Level-1 trigger system in order to maintain an
acceptable trigger rate. To extract the track information at the
required latency – few microseconds - a dedicated hardware has to be
used. We present the tests of a prototype system based on...
Jianmeng Dong
(Universite Libre de Bruxelles (BE))
9/29/15, 5:27 PM
Trigger
Poster
We developed a new AMC board based on AMC.0, named as Trigger Receiver Board (TRB). TRB is a high bandwidth data-stream processor, using one Xilinx Artix-7 FPGA. This FPGA has 16 MGTs running up to 6.4Gbps, making TRB capable to handle total bandwidth up to 100 Gbps. Also there are LVDS I/Os routed to a FMC connector for commercial extend board and two micro connectors for MicroZED. One...
Dr
Wojciech Zabolotny
(University of Warsaw (PL))
9/29/15, 5:28 PM
Trigger
Poster
The CMS experiment is currently undergoing upgrade of its trigger, including the Level-1 muon trigger. In the barrel-endcap transition region it is necessary to merge data from 3 types of detectors - RPC, DT and CSC. The Overlap Muon Track Finder (OMTF) uses the novelty approach to concentrate and process those data in an uniform manner. The paper presents the algorithm and FPGA firmware...
Othmane Rifki
(University of Oklahoma (US))
9/29/15, 5:29 PM
Trigger
Poster
The ATLAS readout architecture uses the concept of Regions of Interest (RoIs) identified by the hardware trigger for further analysis in trigger software. The High Level Trigger uses these RoIs to guide the retrieval of information from the readout system. Currently, a custom VME system, the RoI Builder (RoIB), collects the RoIs at 100 kHz. This talk describes the evolution of the RoIB to a...
23.
Development of a sub-nanosecond time-to-digital converter based on field-programmable gate array
Yuta Sano
(Nagoya University (JP))
9/29/15, 5:40 PM
Logic
Poster
We present the design and the performance of a 24 channel time-to-digital converter with a variable time binning of down to 0.39 nsec based on a Xilinx Kintex-7 field-programmable gate array. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with external reference clock. The differential and integral nonlinearities have been measured to be less...
Dr
Wojciech Zabolotny
(Warsaw University of Technology, Institute of Electronic Systems (PL))
9/29/15, 5:41 PM
Logic
Poster
The Data Processing Boards (DPB) are an important component of the CBM
readout chain.
Before the final, production versions of DPB may be designed, it is
important to create a prototyping platform, to test and select appropriate
hardware and firmware solutions.
The Kintex based AMC FMC Carrier (AFCK) board is a versatile and open
solution fulfilling those requirements, offering...
Jinyuan Wu
(Fermi National Accelerator Lab. (US))
9/29/15, 5:43 PM
Logic
Poster
In underground neutrino experiments, waveform digitization is often demanded at Giga-samples per second with occasional possible high instantaneous hit rate up to MHz range. As an alternative of regular flash ADC, a fast turn-on ADC scheme is presented in this paper. The ADC hibernates most of time during normal operation when the PMT is not hit and wakes up immediately to digitize the...
Dr
Michele Caselle
(KIT)
9/29/15, 5:45 PM
Logic
Poster
A growing number of physics experiments requires DAQ systems with multi-Gbytes/s data-links. We developed a Direct Memory Access (DMA) engine compatible with the Xilinx PCI Express Gen2/3 core. The design comes with a Linux driver. Preliminary measurements with a Gen3 single-core have reached a throughput of up to 6.7 GBytes/s. We also intend to use this technology for direct communication...
Paolo Durante
(CERN)
9/29/15, 5:46 PM
Logic
Poster
The experiments at the LHC are undergoing a massive design upgrade to increase their data-taking capacities in the coming years, in anticipation of higher luminosity and new running conditions. For some experiments, the requirement of 100Gbps of readout bandwidth per readout unit has driven the adoption of PCI-express Gen3 as the main readout protocol. Limitations of current FPGA silicon to 8...
Ales Svetek
(University of Wisconsin (US))
9/29/15, 5:47 PM
Logic
Poster
The CMS Phase 1 Calorimeter Trigger Upgrade Layer-1 CTP7 Card
installation, commissioning and operation are described. The
monitoring and performance of this system and interfaces are
also covered.
Marcel Zeiler
(CERN)
9/29/15, 5:58 PM
Opto
Poster
A silicon photonic chip for radiation resistance evaluations has been designed and is currently being fabricated in an ePIXfab multi-project wafer run at imec. The chip contains custom-designed Mach-Zehnder modulators, pre-designed “building-block” modulators and photodiodes as well as various passive test structures. The simulation of the custom Mach-Zehnder modulators and the design flow of...
Alex Grillo
(University of California,Santa Cruz (US))
9/29/15, 5:59 PM
Opto
Poster
Data transmission requirements for the upgrade of the ATLAS Pixel detector will be difficult to meet. The expected trigger rate and occupancy imply multi-gigabit per second transmission rates but radiation levels immediately at the detector preclude completely optical solutions. Electrical transmission for a short distance will be necessary to move optical components to a safer area. We...
Piotr Skwierawski
(KIT)
9/29/15, 6:00 PM
Opto
Poster
Current and future particle physics or photon science detectors easily generate raw data rates of hundreds of Tbit/s. Even with massive local data reduction these data cannot be read out with current optical links. We propose a new optical data transmission system based on wavelength division multiplexing (WDM) with multiple monolithically integrated Mach-Zehnder modulators and optical...
Datao Gong
(Southern Methodist Univeristy)
9/29/15, 6:01 PM
Opto
Poster
MTx is a dual-channel optical transmitter. MTRx is a transceiver. They are custom developed, small form-factor, low mass and radiation tolerant for detector front-end in particle physics. A custom light-coupling fixture connects fibers of LC ferrules. MTx and MRTx are board-mount and 5.9 mm tall. The driver ASIC is LOCld developed for the ATLAS Liquid Argon Calorimeter trigger upgrade. The...
Mark Istvan Kovacs
(CERN)
9/29/15, 6:12 PM
Packaging
Poster
The CMS tracker upgrade at HL-LHC relies on hybrid modules build on high density interconnecting flexible circuits. They contain several readout ASICs having high speed digital ports required for configuration and data readout, implemented as SLVS differential pairs. This paper presents the connectivity requirements on the CMS tracker hybrids; it compares several transmission line...
Dr
Michele Caselle
(KIT - Karlsruhe Institute of Technology (DE))
9/29/15, 6:13 PM
Packaging
Poster
Karlsruhe Institute of Technology (KIT) is one of the module production centres for the upgrade of the CMS pixel detector (phase 1). We will present recent developments of high-density low-cost bump-bonding technologies for both single prototype ICs and mass-production. In addition we will discuss our latest results on high-density copper pillar, gold-stud and Precoat-by-Powder Sheet (PPS)...
Prof.
Joseph Izen
(University of Texas at Dallas)
9/29/15, 6:14 PM
Packaging
Poster
Unencapsulated aluminum wedge wire bonds are common in particle-physics pixel and strip detectors. Industry-favored bulk encapsulation is eschewed due to the range of operating temperatures and radiation. Wire bond failures are a persistent, source of tracking detector failure Unencapsulated bonds are vulnerable to condensation-induced corrosion, particularly when halides are present....
17.
Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector
Flavio Loddo
(INFN-BARI)
9/30/15, 4:30 PM
ASICs
Poster
In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time to fully integrate the detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A...
115.
Development and experimental study of the Read-out ASIC for Muon Chambers of the CBM Experiment
Mr
Evgeny Malankin
(NRNU MEPhI)
9/30/15, 4:30 PM
ASICs
Poster
The measurement results of the front-end ASIC for GEM detectors for Muon Chambers in the CBM experiment are presented. The MUCH ASIC was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators were measured. The channels provide a sufficient dynamic range...
Robert Szczygiel
(AGH University of Science and Technology)
9/30/15, 4:31 PM
ASICs
Poster
We present a flexible, high speed readout system for the high-frame-rate photon-counting ASICs. The solution was implemented in an ASIC with 128 x 256 pixel matrix with dual 14-bit counter pixels, in 130 nm CMOS technology. In the presentation the details of the architecture and the test results will be shown. Currently the ASIC runs stable with 200 MHz input clock, while the tests with 500...
Prof.
Jinghong Chen
(University of Houston)
9/30/15, 4:32 PM
ASICs
Poster
This paper presents a 12-bit 60-MS/s SHA-less opamp-sharing pipeline analog-to-digital converter implemented in a 0.13-µm CMOS technology. A switch-embedded dual-input current-reused operational transconductance amplifier with an overlapping two-phase clocking scheme is proposed to achieve low power and eliminate memory effects. The ADC achieves a signal-to-noise and distortion ratio of 64.9...
Mrs
Evgenia Voulgari
(CERN)
9/30/15, 4:33 PM
ASICs
Poster
An ultralow leakage current Application Specific Integrated Circuit (ASIC) called Utopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 $\mu$m CMOS, in order to be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology of a Current to Frequency Converter (CFC) and demonstrates a wide dynamic range of almost 7 decades without range...
Ennio Monteil
(Universita e INFN Torino (IT))
9/30/15, 4:34 PM
ASICs
Poster
Pixel detectors for HL-LHC experiments require the development of a new generation front-end chip to stand unprecedented radiation levels, very high hit rates and increased pixel granularity. A very compact, low power, low threshold very front-end design in 65nm CMOS technology is described. It contains a synchronous comparator with output offset storage threshold compensation technique. The...
Datao Gong
(Southern Methodist Univeristy)
9/30/15, 4:35 PM
ASICs
Poster
We present the design and test results of LOCx2, a high-speed serializer ASIC for detector readout in the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels. Each encodes the ADC data with an overhead of 12.5% and transmits serial data at 5.12 Gbps. The ASIC is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology and is packaged using QFN100....
Elia Conti
(CERN)
9/30/15, 4:36 PM
ASICs
Poster
The SystemVerilog-UVM simulation and verification platform VEPIX53, developed by the RD53 collaboration, is being used for the study and optimization of digital pixel chip architectures at behavioral level. The stimuli used by the framework can be generated internally using pre-defined hit classes or can also be imported from external CMS and ATLAS Monte Carlo detector simulations, featuring...
Dr
Tommaso Vergine
(University of Pavia)
9/30/15, 4:37 PM
ASICs
Poster
The presented 12bit single slope ADC is part of a system (called GBT-SCA), aimed to sense and monitor electrical/physical parameters in the LHC experiments. Measurement accuracy has been achieved by the combination of an analog accurate ramp generation and a digital correction for offset and gain errors. Moreover, both analog and digital solutions have been adopted to guarantee rad-hard...
Dr
Tomasz Fiutowski
(AGH University of Science and Technology (PL))
9/30/15, 4:38 PM
ASICs
Poster
One of the major problems that have to be addressed in the design of the front-end electronics for readout of MPGDs, is its resistance to possible random discharges inside active detector volume. This issue becomes particularly critical for the electronics built as ASICs implemented in a modern CMOS technology, for which the breakdown voltages are in the range of a few Volts, while the...
Krzysztof Piotr Swientek
(AGH University of Science and Technology (PL))
9/30/15, 4:39 PM
ASICs
Poster
Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout 128-channel ASIC called SALT. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130~nm process and uses a novel architecture comprising of analog front-end and ultra-low power ($<$0.5~mW) fast (40~MSps)...
Jakub Moron
(AGH University of Science and Technology (PL))
9/30/15, 4:40 PM
ASICs
Poster
The design and the preliminary measurements results of two ultra-low power 10-bit Successive Approximation Register (SAR) Analog to Digital converters (ADC) fabricated in two CMOS 130~nm technologies (process A and B) are presented and compared. Both prototypes are fully functional achieving a good linearity, with INL and DNL below 1~LSB, and a good effective resolution, with ENOB above 9...
Tomasz Hemperek
(Universitaet Bonn (DE))
9/30/15, 4:41 PM
ASICs
Poster
The LHC Phase-II upgrade will lead to a significant increase in luminosity, which will bring new challenges for the operation of the inner tracking detectors. To handle those requirements, a new pixel readout chip is being developed, within the RD53 collaboration taking advantage of the reduced feature size of 65nm technology. A 64x64 pixels (50 um pitch) prototype chip, introducing the...
Daryl Hare
(Fermi National Accelerator Lab. (US))
9/30/15, 4:42 PM
ASICs
Poster
The CMS experiment at the CERN Large Hadron Collider will upgrade the photon detection and readout systems of its barrel and endcap hadron calorimeters (HCAL) through the second long shutdown of the LHC in 2018. A central feature of this upgrade is the development of two new versions of the QIE (Charge Integrator and Encoder), a Fermilab-designed custom ASIC for measurement of charge from...
Deepak Gajanana
(NIKHEF)
9/30/15, 4:43 PM
ASICs
Poster
In the ALICE ITS upgrade project[1], serial powering of the modules of the detector is proposed. Serial powering scheme has its own advantages: It brings power at low currents and high voltage drastically reducing material budget. Serial powering of detectors has been proposed before[2]. A shunt LDO is designed for this purpose to regulate the power. The ITS is in radiation environment (~100...
Piotr Maj
(AGH UST)
9/30/15, 4:53 PM
Systems
Poster
We present X-Ray camera consisting of hybrid pixel detector working in SPC mode. The camera consists of hybrid pixel detector built from silicon sensor and two readout integrated circuits, each of which is a matrix of 128 x 256 pixels with 75µm pitch, designed in CMOS 130 nm. The camera communicates with the higher level system using Ethernet, USB 2.0 and a Camera Link (up to 640 MB/s). An...
David Calvo
(IFIC)
9/30/15, 4:55 PM
Systems
Poster
The KM3NeT Collaboration aims at the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean Sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The readout and data acquisition system of KM3NeT has to collect, treat and send to shore, the enormous amount of data produced by the photomultipliers and the...
Mr
Michael Wiebusch
(Goethe Universität, Frankfurt)
9/30/15, 4:56 PM
Systems
Poster
Reconstructing Open-Charm Particles with the CBM-Experiment requires an ultra-light
Micro Vertex Detector (MVD) using CMOS Monolithic Active Pixel Sensors.
These sensors have unique properties concerning spatial resolution, radiation hardness,
and material budget. A full read-out chain was designed and prototyped,
comprising a multi-purpose FPGA platform and specialized front-end...
Khilesh Pradip Mistry
(University of Pennsylvania (US))
9/30/15, 4:57 PM
Systems
Poster
The ATLAS Transition Radiation Tracker (TRT) is a gaseous drift tube tracker which combines continuous tracking capabilities with particle identification based on transition radiation. The TRT Data Acquisition system uses custom front-end ASICs and boards for trigger and timing control as well as data read-out. To prepare for LHC run 2, changes were made to support the increased ATLAS trigger...
Julian Maxime Mendez
(CERN)
9/30/15, 4:58 PM
Systems
Poster
The MicroTCA (MTCA) and AdvancedTCA (ATCA) industry standards have been selected as the hardware platform for the upgrade of the electronic systems of some experiments of the Large Hadron Collider (LHC). In this context, the electronics support group for experiments at CERN is running a technical evaluation project for xTCA equipment. As part of this activity, a commercial solution for an...
Heiko Engel
(Johann-Wolfgang-Goethe Univ. (DE))
9/30/15, 4:59 PM
Systems
Poster
The ALICE High Level Trigger (HLT) is a computing cluster dedicated to the online reconstruction and compression of experiment data. The interfaces to the HLT are realized with FPGA based PCIe boards. HLT has replaced all of its previous interface boards with the Common Read-Out Receiver Card (C-RORC).
This contribution describes the ALICE HLT C-RORC firmware upgrade for Run2, the extended...
Oliver Holme
(ETH Zurich (CH))
9/30/15, 5:01 PM
Systems
Poster
The Detector Control System (DCS) of the CMS Electromagnetic Calorimeter (ECAL) has undergone significant improvements during the first LHC Long Shutdown (LS1). Based on the experience acquired during the first period of physics data taking of the LHC, several hardware projects were carried out to improve data accuracy, to minimise the impact of failures and to extend remote control...
Lorenzo Cassina
(Universita & INFN, Milano-Bicocca (IT))
9/30/15, 5:02 PM
Systems
Poster
This presentation is meant to summarize the photon detector chain designed for the Upgraded RICH detector for the LHCb experiment. The photosensitive surface is composed of 64-channel MaPMTS (R11265 or R12699, produced by Hamamatsu) coupled with an external read-out electronics. The front-end chip, the CLARO, is an 8-channel ASIC in AMS 0.35 $\mu$m CMOS technology. The CLARO is able to sustain...
Dr
Scott Daniel Kolya
(ESS - European Spallation Source (SE))
9/30/15, 5:03 PM
Systems
Poster
The European Spallation Source (ESS) will be
multi-disciplinary research centre based on
the world’s most powerful neutron source.
This new facility will be around 30 times
brighter than today's leading facilities,
enabling new opportunities for researchers
in the fields of life sciences, energy,
environmental technology, cultural heritage
and fundamental physics.
We summarise the...
Rui Gao
(University of Oxford (GB))
9/30/15, 5:04 PM
Systems
Poster
The TORCH detector is an R&D project to provide low-momentum particle identification, combining Time-Of-Flight and Cherenkov techniques to achieve pi/K separation up to 10 GeV/c. Based-on an existing scalable design, we have undertaken production and testing of a system and have instrumented a novel customized Micro Channel Plate (MCP) device with 128-channels. The development and the...
Yifan Yang
(Universite Libre de Bruxelles (BE))
9/30/15, 5:05 PM
Systems
Poster
New Gas Electron Multiplier (GEM) based detectors are developed in view of the forward muon system upgrade of the CMS experiment in Phase 2 of the LHC. With the prospective of the full installation of the detectors during the LHC long shutdown (LS) 2 in 2018/2019, a slice test will take place during the Year-End Technical Stop of 2016 with subsequent detector commissioning. This contribution...
Karol Hennessy
(University of Liverpool (GB))
9/30/15, 5:06 PM
Systems
Poster
The upgraded LHCb VELO (vertex detector) will be equipped with
silicon hybrid pixel detectors reading out at 40 MHz. The high data rates
will be handled by high-end computing servers installed with FPGA cards.
The output stage of the ASIC will be equipped with a custom developed
output serialiser capable of handling the high rates while operating
at low power. The firmware development...
Jubin Mitra
(Department of Atomic Energy (IN)),
Shuaib Ahmad Khan
(Department of Atomic Energy (IN))
9/30/15, 5:07 PM
Systems
Poster
The high-energy physics experiments at the CERN’s Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2020. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver)1 links. The present work discusses the GBT link performance...
Michal Husejko
(CERN)
9/30/15, 5:08 PM
Systems
Poster
The current production version of the CMS ECAL Data Concentrator Card (DCC) is implemented with 11 FPGA devices (Altera and Xilinx), all placed on a single 9U VME card. The development and verification of the DCC FPGA firmware have consumed considerable amount of engineering resources. We have observed in recent years a trend in availability of new engineering tools for FPGA programming. Most...
Nathaniel Joseph Pastika
(Baylor University (US))
9/30/15, 5:09 PM
Systems
Poster
The CMS experiment at the CERN Large Hadron Collider (LHC) will upgrade the photon detection and readout systems of its hadron calorimeters (HCAL) through the second long shutdown of the LHC in 2018. The upgrade includes new silicon photomultipliers (SiPMs), SiPM control electronics, signal digitization via the Fermilab QIE11 ASIC, data formatting and serialization via a Microsemi FPGA, and...
Nikitas Loukas
(University of Ioannina (GR))
9/30/15, 5:19 PM
Trigger
Poster
The CMS Drift Tube Track Finder (DTTF) is being upgraded to a uTCA system, called Muon Barrel Track Finder (MBTF), so that it can cope with the high backgrounds which are expected at high luminosity and high pile-up. This upgrade which further improves the reliability of the system will be commissioned for the LHC RUN-II. In contrast to the DTTF, the MBTF receives muon super-primitives which...
Mr
Leonid Epshteyn
(Budker Institute of Nuclear Physics)
9/30/15, 5:20 PM
Trigger
Poster
For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP) near threshold is necessary to measure the particles flight time in the LXe calorimeter with accuracy of about few nanosecond. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the...
Andrea Biagioni
(INFN)
9/30/15, 5:21 PM
Trigger
Poster
A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power.
To ensure the real-time operation of the system, a dedicated data transport mechanism has been implemented: an FPGA-based Network...
224.
Pulsar IIb Design, System Integration and Next-Generation Full Mesh ATCA Backplane Test Results
Jamieson Olsen
(Fermilab)
9/30/15, 5:23 PM
Trigger
Poster
The Pulsar IIb is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this talk we describe the Pulsar II hardware, our full-crate integration tests,...
Jamieson Olsen
(Fermilab)
9/30/15, 5:24 PM
Trigger
Poster
Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track finding algorithms. PRAM implementation has been mostly done with ASIC for high pattern density. However, implementation of PRAM in FPGAs allow for quick iterations, making it an ideal hardware platform for designing and evaluating new PRAM features...
Nicola De Simone
(Universita e INFN Roma Tor Vergata (IT))
9/30/15, 5:25 PM
Trigger
Poster
The Liquid Krypton calorimeter of the NA62 experiment at the CERN SPS
is an essential part of the photon-veto system. The Level-0 trigger
of the calorimeter identifies electromagnetic clusters and provides
their position, fine-time and energy information for the trigger decision.
In this contribution we present the first results and performances of the full system during the physics...
Johannes Wittmann
(Austrian Academy of Sciences (AT))
9/30/15, 5:26 PM
Trigger
Poster
The Global Trigger is the final step of the CMS Level-1 Trigger. Previously implemented in VME, it has been redesigned and completely rebuilt in microTCA technology, using the Virtex-7 FPGA chip family. It will allow to implement trigger algorithms close to the final physics selection. The new system is presented, together with performance tests undertaken in parallel operation with the legacy...
47.
Results from longevity studies of the on-detector readout of the CMS Electromagnetic calorimeter
Michael Planer
(University of Notre Dame (US))
9/30/15, 5:27 PM
Radiation
Poster
The on-detector readout installed in the CMS Electromagnetic Calorimeter (ECAL) has been tested to resist the radiation environment expected for ten years of LHC operation. The Phase II upgrade programme of CMS foresees additional LHC operation at higher luminosities until about 2035. Qualification of the on-detector readout for this longer running time, for the existing electronics and for...
Chengxin Zhao
(University of Oslo (NO))
9/30/15, 5:28 PM
Radiation
Poster
This paper presents the radiation monitoring system on the Readout Control
Unit (RCU) of the the ALICE TPC Front End Electronics. In Run 1, Single
Event Upsets (SEUs) in the configuration memory of the SRAM based FPGA
were counted, and the results from different run periods with stable beam condi-
tions are presented. For Run 2, a new RCU has been designed where the number
of SEUs in...
Oliver Bitterling
(Technische Universitaet Darmstadt (DE))
9/30/15, 5:29 PM
Radiation
Poster
The increase of the Large-Hadron-Collider (LHC) luminosity over the next years will also increase the levels of ionizing radiation in the accelerator surroundings. Critical systems like the QPS need to be upgraded for higher radiation tolerance. A high resolution ADC for a future QPS component was tested for its radiation tolerance using a 230MeV proton beam up to a dose of 3.4kGy. The error...
Helio Takai
(Brookhaven National Laboratory (US))
9/30/15, 5:31 PM
Radiation
Poster
The analog to digital converter (ADC) is a component that is widely used in high energy physics. In recent years commercial off the shelf ADCs has become increasingly tolerant to ionizing radiation, likely a side effect of their implementation as a small feature size integrated circuit. In this presentation we report on recent irradiation results of COTS ADCs that can potentially be used in...
Alexandre Zabi
(Centre National de la Recherche Scientifique (FR))
9/30/15, 5:32 PM
Poster
The design of the upgraded CMS Level-1 calorimeter trigger is based on a novel concept the Time Multiplexed Trigger (TMT). In this design there are nine main processing nodes each of which receives the data from an entire event. The nine processing nodes are fed data from a TMT switch which consists of 36 processors whose job is to collect fragments of events from each bunch crossing and...
Massimo Lazzaroni
(Università degli Studi e INFN Milano (IT))
9/30/15, 5:42 PM
Power
Poster
The research activity for the design of the power distribution section of the ATLAS LAr Trigger Digitizer Board board (LTDB) will be presented. Many aspects concerning the radiation hardness and the ability to operate Point-of-load converters even in presence of high magnetic fields will be covered. Devices designed by CERN have been used and their capability for implementation on the ATLAS...
Francois Vazeille
(Univ. Blaise Pascal Clermont-Fe. II (FR))
9/30/15, 5:43 PM
Power
Poster
The experience gained in the working of the present High Voltage system of the Tile calorimeter and the new HLLHC constraints, in particular the increase in radiation, lead to the proposal of moving the embedded regulation system to a remote system in the counting room. This system is using the same regulation scheme as the present one and distributes the individual high voltage settings with...
Ryan Christopher Edgar
(University of Michigan (US))
9/30/15, 5:44 PM
Power
Poster
The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the forward region of the ATLAS detector. The large Low Voltage power demands necessitate a point-of-load architecture with on-detector power conversion. We present final results from an extensive campaign to test commercial power devices in radiation and magnetic fields, and describe an alternate...
Dr
Pablo Fernandez Martinez
(IMB-CNM (CSIC))
9/30/15, 5:45 PM
Power
Poster
This work presents a new silicon vertical JFET technology, based on the trenched 3D detectors developed at CNM, to be used as switches for the HV powering scheme of the ATLAS upgrade Inner Tracker. An optimization of the device characteristics is performed by TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific...
Katja Klein
(Rheinisch-Westfaelische Tech. Hoch. (DE))
9/30/15, 5:46 PM
Power
Poster
The CMS pixel detector will be exchanged during the technical stop 2016/2017. To allow the new pixel detector to be powered with the legacy cable plant and power supplies, a novel powering scheme based on DC-DC conversion is employed.
After the successful conclusion of an extensive development and prototyping phase, mass production of 1800 DC-DC converters and power-related PCBs has started...
Jose Luis Sirvent Blasco
(University of Barcelona (ES))
9/30/15, 5:57 PM
Production
Poster
A secondary particle shower acquisition system is under design for the CERN beam wire scanners upgrade. The new acquisition system is based on a polycrystalline diamond detector. Beam synchronous digitization will be performed in the tunnel, near the detector to fully exploit its large dynamic range and fast response. Two integrator ASICs (ICECAL and QIE10) are being characterized and compared...
Adriana Voto
(Ministere des affaires etrangeres et europeennes (FR))
9/30/15, 5:58 PM
Production
Poster
Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex, having a direct impact on its availability. They must be designed to achieve a high Mean Time Between Failure (MTBF) and hardware reliability must be ensured by board level testing before hardware is assembled and installed. In this framework, the National Instrument PCI...
