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Summary
We have successfully designed a highly integrated sensor for direct charge collection in the XFAB CMOS 1P4M process. The sensor collects the electrons drifting to the top metal placed on the top of each pixel by adding strong electric field. The electric field is formed by adding high voltage between the top metal which is the electron collection node and another off-chip plate. No post processing is necessary. Two readout modes have been designed in the readout system. One is called analog channel, which is composed of a low-noise and low-power charge sensitive amplifier (CSA) with a feedback 5fF capacitor, two stage source followers and an analog buffer. The differential architecture is proposed in the CSA. Therefore, the CSA can be adjusted the operation point for different applications. The source follower stage is much important to isolate the low power CSA from the switches effect. In order to decrease the chip area and power consumption, the analog buffer is sharing with the whole pixel array. The traditional rolling shutter architecture is proposed in the analog channel. It achieves an integration time of 259.2us. The other is called digital channel, based on an in-pixel binary front-end with hit-driver circuit. In the digital channel, a binary hit-data readout architecture with zero suppression in the matrix has been developed. This architecture consists of the Reset-decoder and address-encoder circuit, only reading hit pixels. It allows lower power consumption and lower integration time. Additional, a 4-bit in-pixel DAC is applied to the input node of the in-pixel comparator. It is used to calibrate the total offset of the CSA and comparator caused by the devices mismatch, hence decreasing the system threshold spread.
The CSA benefits from high gain by using a small feedback capacitor. It achieves a gain of 320mV/fC with 1uW power consumption. The ultra-low power dissipation significantly decreases the total power consumption of the chip. The preliminary test results confirm the low-noise and low-power readout circuit. The ENC of the proposed front-end circuit is 30e- rms at a 5us peaking time with a detector capacitance of 23fF. The direct charge collection capability of the TopMetal2-, without any post processing, makes the overall integration cost much lower than for example the technologies used in producing the hybrid solid- state detectors.
Further improvements are investigated after this iteration: reducing the feedback capacitor value to increase the gain of CSA hence the signal to noise ratio, optimize electrons collection top metal size and shape to reduce the detector input capacitance. We will present the Overall architecture, the detailed design and testing results of the TopMetal2- chip in the conference.
