A two stage upgrade of the MBTF is foreseen. In the first stage the barrel track-finding hardware platform is upgraded using twelve MP7 cards employing Xilinx Virtex-7 FPGAs which can receive and transmit data at 10 Gb/s from 72 input and 72 output fibers. In contrast to the legacy DDTF system the trigger primitives for the MBTF are formed using both DT and RPC data (BMTF super-primitives). However, the legacy track finding algorithms are used on the MP7 processors. The new framework results in a far more robust trigger system which is expected to perform better than the legacy system. Most importantly, the hardware capabilities in terms of algorithm capacity and speed have been dramatically enhanced so that this system becomes ready for the algorithm (firmware) upgrade which will come later during the second stage. To study the performance of the MBTF, simulation and real data have been used. Events from Monte Carlo simulation with muon tracks have been injected at the inputs of the MBTF. The results at the output of the MBTF have been compared with those of the C++ emulator model to study the performance of the hardware. Furthermore the new electronics have been implemented to a slice of the RPC and DT detector and cosmic ray and pp data have also been used to study tin detail performance of the new system.
During the second stage, when results from algorithm studies at high luminosity and high pile-up are finalized, the algorithm firmware will be upgraded to enhance the system capabilities. The data-distribution and the design of the algorithms which will handle the super-primitive data will depend on results from studies, which have started.