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Description
Summary
A Liquid Argon Calorimeter (LAr) Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS LAr trigger electronics, which will be commissioned in 2017-2018. Each LDTB includes 320-channel analog amplifiers, 80 quad-channel 12-bit 40 MS/s Analog to Digital converter (ADCs), 20 dual-channel 5.12 Gbps per channel transmitters (LOCx2’s), and 20 optical transmitter modules (MTx’s). Both the ADC and LOCx2 need a 40-MHz clock signal that is synchronized to the LHC bunch-crossing clock. The ADC, LOCx2, and MTx need to be configured remotely. The operational status of LTDB needs to be monitored from the back end. It is critical to design a clock and control system for the LTDB. In this paper, we present the design and the evaluation of the clock and control system of the LTDB.
The clock and control system use four duplex optical links between each LTDB at the front end and the GBT Driver (GBTD) board operated at the back end. Each duplex link, which serves ¼ LTDB, includes an optical transceiver module MTRx, a transceiver ASIC GBTX, and a GBT Slow Control Adapter (SCA) on the LTDB. The optical links use commercial multi-channel optical transceivers and Multi-Gigabit-Transceiver-embedded FPGAs on the GBTD.
All the clock signals on the LTDB come from the recovered clocks of GBTX. In the current clock and control system design, each GBTX provides 40-MHz clocks to 20 ADCs and 5 LOCx2’s on ¼ LTDB. Jitter and skew, which are important characteristics for the ADC and LOCx2, of the recovered clocks of GBTX are being evaluated. The measurement results will be presented in the full paper.
The control of LTDB includes the following four functions. First, via SCA I2C channels, the internal registers of ADCs, LOCx2’s, and MTx’s can be written to set initial configurations and be read back to monitor the operational status. Each SCA controls 20 ADCs, 5 LOCx2’s, and 5 MTx’s. Second, an e-port data output of GBTX is used to reset the bunch crossing identification (BCID) counter of each LOCx2 every 3564 bunch-crossing clock cycles. Each GBTX provides the BCID reset signals to 5 LOCx2’s. Third, we use the general-purpose I/O bus of GBT SCA to turn on or off DC-DC converter modules FEASTMP/N which provides supply voltages for the analog amplifiers, ADCs, LOCx2’s and MTx’s. Finally, we use GBT SCA ADC channels to monitor power supply voltages, power supply currents, and temperatures on the LTDB.
Two evaluation boards, one including an MTRx, a GBTX and a GBT SCA and the other including 4 ADCs, a LOCx2, and an MTx, are being developed to evaluate the clock and control system. The evaluation results will be presented in the full paper.
