28 September 2015 to 2 October 2015
Lisbon
Europe/Zurich timezone

The New Front-End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

29 Sep 2015, 17:11
1m
Hall of Civil Engineering (Lisbon)

Hall of Civil Engineering

Lisbon

IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal
Poster Systems Poster

Speaker

Agostinho Da Silva Gomes (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

Description

The Tile Calorimeter (TileCal) is the main hadronic calorimeter of the ATLAS experiment. TileCal will undergo a major replacement of its readout electronics for the upgrade of the LHC in 2024. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. Three different options are presently being investigated for the front-end electronic upgrade. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, has been built.

Summary

We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features, including power system redundancy, data processing redundancy, 10 Gbps optical links, and a Kintex-7 FPGA with single-event upset mitigation. To date, we have built a Demonstrator – a fully-functional prototype of the new system. Performance results, radiation tolerance measurements, and plans going forward will be presented.

Primary author

Presentation Materials