28 September 2015 to 2 October 2015
Lisbon
Europe/Zurich timezone

Commissioning of the Upgraded CSC Endcap Muon Port Cards at CMS

29 Sep 2015, 17:23
1m
Hall of Civil Engineering (Lisbon)

Hall of Civil Engineering

Lisbon

IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal
Poster Trigger Poster

Speaker

Mr Mikhail Matveev (Rice University)

Description

We report on the status of commissioning of the upgraded Muon Port Cards in the Level 1 Trigger electronic system serving the Endcap Cathode Strip Chamber (CSC) sub-detector at the CMS experiment at CERN. After presenting an overview of the existing system and upgrade requirements, we describe the new Muon Port Card FPGA mezzanine and its firmware developed to drive the new 3.2Gbps optical links. Results of initial tests with the existing and upgraded CSC Track Finder boards and further plans are given in the concluding sections.

Summary

There are 180 1.6Gbps optical links from 60 Muon Port Cards (MPC) to the Cathode Strip Chamber Track Finder (CSCTF) in the original system. Before its upgrade the MPC was able to provide up to three trigger primitives from a cluster of nine CSC chambers to the Level 1 CSCTF. With an LHC luminosity increase to 1035 cm-2s-1 at full energy of 7TeV/beam the simulation studies suggest that we can expect 2-3 times more trigger primitives per bunch crossing from the front-end electronics. To comply with this requirement, the MPC, CSCTF, and optical cables need to be upgraded. The upgraded MPC allows to transmit all the 18 trigger primitives from the peripheral crate. This feature would allow us to search for physics signatures of muon jets that require more trigger primitives per trigger sector. At the same time, it is very desirable to preserve all the old optical links for compatibility with the older Track Finder during transition period at the beginning of Run 2. Installation of the upgraded MPC boards along with the new optical cables has been completed at the CMS in the summer of 2014. We describe the final design of the new MPC mezzanine FPGA, its firmware, and results of the laboratory and in situ tests with the old and new CSCTF boards.

Primary authors

Mr Alex Madorsky (University of Florida) Mr Jamal Rorie (Rice University) Mr Jinghua Liu (Rice University) Mr Karl Ecklund (Rice University) Mr Mikhail Matveev (Rice University) Mr Paul Padley (Rice University)

Presentation Materials

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