28 September 2015 to 2 October 2015
Lisbon
Europe/Zurich timezone

65k pixel X-Ray camera module of 75µm pixel size

30 Sep 2015, 16:53
1m
Hall of Civil Engineering (Lisbon)

Hall of Civil Engineering

Lisbon

IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal
Poster Systems Poster

Speaker

Piotr Maj (AGH UST)

Description

We present X-Ray camera consisting of hybrid pixel detector working in SPC mode. The camera consists of hybrid pixel detector built from silicon sensor and two readout integrated circuits, each of which is a matrix of 128 x 256 pixels with 75µm pitch, designed in CMOS 130 nm. The camera communicates with the higher level system using Ethernet, USB 2.0 and a Camera Link (up to 640 MB/s). An Artix-7 FPGA is used for both Camera Link interface and integrated circuit specific communication at the frequency of up to 200MHz – programmed in single software platform.

Summary

We present a X-Ray camera module consisting of a hybrid pixel detector working in single photon counting mode. The camera consists of square-shaped, 2 cm x 2 cm hybrid pixel detector built from a single 320 or 450 µm thick silicon sensor designed and fabricated by Hamamatsu and two readout integrated circuits, each of which is a matrix of 128 x 256 pixels with 75µm pitch, designed in CMOS 130nm at AGH-UST. The camera communicates with the higher level system using one of the interfaces including Ethernet (UDP), USB 2.0 and a Camera Link for high-speed data streaming up to 640 MB/s while having single 5V power supply connector. A commercially available sbRIO 9651 module containing an Artix-7 FPGA is used for both Camera Link interface and integrated circuit specific communication at the frequency of up to 200MHz. In the design of the camera functionality a single software platform was used for FPGA, Real-time OS and a host application allowing high acceleration of the development process.
During presentation a silicon pixel detector readout circuit architecture will be presented including single channel architecture, threshold dispersion trimming capabilities and high-count rate performance. The camera design will be shown with the details of FPGA and Real-time application written in single software platform without any significant limitations.

Primary author

Piotr Maj (AGH UST)

Co-authors

Ms Anna Kozioł (AGH UST dep. Measurement and Electronics) Krzysztof Kasiński (urn:Google) Pawel Grybos (AGH University of Science and Technology) Robert Szczygiel (AGH UST)

Presentation Materials

There are no materials yet.