28 September 2015 to 2 October 2015
Europe/Zurich timezone

Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of Run-2

2 Oct 2015, 11:00
Grande Anfiteatro (Lisbon)

Grande Anfiteatro


IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal
Plenary Plenary


Marek Palka (Jagiellonian University (PL))


In 2015 the LHC will operate with a higher center-of-mass energy and proton beams luminosity. To keep a high trigger efficiency against an increased event rate, part of ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. The performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is illustrated.


ATLAS is a Large Hadron Collider (LHC) experiment located at the European Centre for Nuclear Research (CERN) in Switzerland. Due to the increase in the LHC instantaneous luminosity up to 3×1034cm−2s−1 and center mass energy (from 7 TeV to 13 TeV) from 2015, the ATLAS Level-1 calorimeter trigger (L1Calo trigger) needs to cope with a higher background rate and the need of keeping the Level-1 trigger rates at high efficiency. The L1Calo trigger designed and commissioned for LHC Run I conditions, made selections on multiplicity of objects (e.g. numbers of jets at various thresholds)
identified in the calorimeters, via sliding window algorithms and Missing Transverse Energy. Such scheme is not designed to handle the higher input rate (about a factor five) in the Real-Time data path from 2015. The upgrade involve all the L1Calo sub-systems:

  • The pre-processor modules (nMCM) has been re-designed by replacing the functionality previously fulfilled by an ASIC with a more flexible Xilinx spartan 6 FPGA. The size of the nMCMC is such to be back compatible in the existing VME crate slot. The new board allow more sophisticated algorithms and improved pedestal subtraction.

  • Jet (JEP) and Clusters (CP) processors have been upgrated in FW only, in particular the backplane data transmission have been increased from 40 MHZ to 160 MHz. This required neverthless a re-design of the merging module (CMX) which are responsible of merging the JEP and CP algorithms results and send it to the central trigger processor (CTP). An additional feature of CMX is to provide the information extracted from JEP and CP via 24 optical links (in several copies) to the new topological processor sub-system (L1Topo).

  • The L1Topo is a new sub-system. It receives data from the calorimeters from 12 CMXs modules but given its flexibility it was adapted to receive input also from the Level-1 muon system. It's an entirely new element of the Level-1 trigger. It's dedicated to perform geometrical cuts, correlations and calculate complex observables as the invariant mass in hardware. L1Topo will then provide an output to the Central Trigger Processor, where the final decision on the acceptance of an event at Level-1 is taken.

This presentation focuses on the commissioning of the upgraded hardware installed during the LHC long shutdown and its performance during the Run 2 initial phase.

Primary author

Marek Palka (Jagiellonian University (PL))

Presentation Materials