Conveners
Programmable Logic, design tools and methods
- Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
Programmable Logic, design tools and methods
- Magnus Hansen (CERN)
Michael Lupberger
(University of Bonn)
29/09/2015, 09:50
Logic
Oral
As proof of principle for a Pixel-TPC, the Timepix ASIC featuring a matrix of 256 x 256 charge sensitive pixels was chosen as anode readout of a gaseous detector. To read out more than a few chips, a new readout system was designed by developing dedicated hardware and FPGA firmware, on which the presentation will focus. The Scalable Readout System, as a general system also used for example in...
Cahit Ugur
(GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE))
29/09/2015, 10:15
Logic
Oral
High precision time measurements are a crucial element in particle identification experiments, which likewise require pulse width information for charge and Time-over-Threshold (ToT) measurements. In almost all of the FPGA-based TDC applications, pulse width measurements are implemented using two of the TDC channels for leading and trailing edge time measurements individually. This method...
Steffen Baehr
(Karlsruhe Institute of Technology)
29/09/2015, 11:10
Logic
Oral
The NeuroBayes machine learning algorithm is deployed for online data reduction at the pixel detector of Belle-II. In order to test, characterize and easily adapt its implementation on FPGAs, a framework was developed. Within the framework a HDL model, written in python using MyHDL, is used for fast exploration of possible configurations. Under usage of input data from physics simulations...