Feb 15 – 19, 2016
Vienna University of Technology
Europe/Vienna timezone

Recent results with HV-CMOS and planar sensors for the CLIC vertex detector

Feb 18, 2016, 2:50 PM
EI7 (Vienna University of Technology)


Vienna University of Technology

Gusshausstraße 27-29, 1040 Wien
Talk Semiconductor Detectors Semiconductor Detectors


Niloufar Alipour Tehrani (Eidgenoessische Tech. Hochschule Zuerich (CH))


The physics aims at a future multi-TeV CLIC linear e+e- collider impose high precision requirements on the vertex detector. The detector also has to match the experimental conditions, such as the time structure of the collisions and the presence of beam-induced backgrounds. The principal challenges are: a point resolution of 3 micron, 10 ns time stamping capabilities, ultra-low mass (0.2% X0 per layer), very low power dissipation (compatible with air-flow cooling) and pulsed power operation. The R&D for the pixel detector follows an integrated approach addressing simultaneously the physics requirements and the engineering constraints. Two types of hybrid pixel detectors with ultra-small pitch (25*25 micron) and analogue readout are explored. Both make use of a dedicated readout ASIC (CLICpix), developed in 65 nm technology. CLICpix is either bump bonded to ultra-thin planar silicon sensors (with and without active edges), or AC coupled through a thin layer of glue to active HV-CMOS sensors. Results of recent beam tests and laboratory calibrations of a variety of assemblies with different sensor thicknesses are presented. Detailed simulations based on Geant4 and TCAD validate the experimental results and serve to optimise the detector design. The R&D project also includes the development of through-silicon via (TSV) technology, as well as various engineering studies involving thin mechanical structures and full-scale air-cooling tests.

Primary authors

Andreas Matthias Nurnberg (CERN) Niloufar Alipour Tehrani (Eidgenoessische Tech. Hochschule Zuerich (CH))

Presentation materials