9-10 July 2015
CERN
Europe/Zurich timezone

The objective of this two days workshop is to increase the competence around code optimization and vectorization. Attendees will learn about hurdles for fully exploiting the multi- and many-core processor architectures, as well as most effective methods to circumvent them. Also, participants will better understand how Intel tools, available to the CERN community, can help them in this process. As a complementary knowledge Intel will provide technical updates on processor architectures. The lectures will be followed by hands-on sessions using the openlab Haswell-EP machines and CERN-wide Intel tools installations, where participants will be able to apply the newly acquired skills to a real-life code, including the code brought by themselves. This event will be lead by experts from Intel teams developing the presented tools.

Pre-requisites

  • Knowledge of Linux
  • Familiarity with the C and C++ programming langages
  • Basic understanding of modern computer architectures, compilers and performance tuning

Speakers

  • Zakhar Matveev (zakhar.a.matveev@intel.com), Intel Advisor team,

  • Georg Zitzlsberger (georg.zitzlsberger@intel.com), Intel Compiler team,

  • Hans Pabst (hans.pabst@intel.com), Intel HPC team.

Feel free to come and ask difficult questions on any topic regarding:

  • Intel tools,
  • compilation,
  • parallelism, vectorization, multithreading,
  • NUMA, COD, caches, architectures,
  • OpenMP.

Intel experts are here to help you! Come and discuss your cases! For the registration, please go to CTA: https://cta.cern.ch/cta2/f?p=110:9:205743002545822::::X_STATUS,X_COURSE_CODE:D,15INW01

 

 

 

Starts
Ends
Europe/Zurich
CERN
Wed room 13, Thu room 11
Technical Training Center