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Description
Summary
Although some components of the present LAr electronics design may be adequate for use in SLHC the lack of spares and elimination of the processes in which the custom ASICs were designed means that the complete ATLAS LAr electronics chain will need to be redesigned for operation at SLHC.
Our work characterizing IBM’s 8WL process has qualified this process for use at much higher levels than required for the LAr electronics ( 300krad ionizing radiation dose and 1013 neutrons/cm**2 fluence) and makes this process an obvious candidate. The ideal behavior of the SiGe bipolar NPN’s and their very low base resistance makes them compelling components to be considered in this low noise wide dynamic range application.
Preamplifier Design- The preamplifier is based on the “super common base” architecture as the one presently installed in the LAr front-end boards described in previous publications. Thanks to the SiGe low spreading base resistance it employs an input transistor of manageable size (emitter length 4 x 20μm, 2 emitter stripe geometry) biased at 8mA collector current. Simulations predict that the preamplifier achieves good integral non-linearity (INL< 1%) and an overall equivalent series noise of ~0.3nV/√Hz while dissipating 42mW.
Shaper Design – It was decided at the outset to use a differential design to help eliminate common mode pickup on and off chip. A series simple translinear configuration was examined and rejected due to its excessive noise. Instead, a differential operational transimpedance amplifier (OTA) gain block followed by a unity gain buffer was implemented using 2.4V PMOS and NPN with 20μm active circuit elements. Since the preamplifier output is at 5V relative to ground , an AC coupling is necessary. One advantage of this approach is that it allowed us to implement a relatively low gain common mode amplifier to maintain a stable DC operating point. The shaper realizes a CR-(RC)2 transfer function, and achieves an input equivalent voltage noise of about 2.2nV/√Hz.
Fabrication - The prototype ASIC fabricated through MOSIS consists of four independently powered preamplifiers and two dual gain shaper stages on a 1.6 X 2.1mm die housed in a 9X9mm open cavity QFN64 package. Packaged ASICS were received in March.
Measurements - All preamp and shaper circuits are functional with gain, shape and dynamic range close to that predicted by SPICE simulation of the extracted layout. Preliminary measurements show good linearity. Work is underway to design a PCB for a complete characterization over the summer.
We intend to discuss the design implementation and measurements of power, linearity, noise and radiation effects.
