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Summary
The currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The constant fraction technique minimizes the time walk effect (dependency of timing on the pulse amplitude). Several attempts have been made to integrate CFD in multi-channel ASICs. But the time resolution measured on the most advanced one is of the order of 30 ps rms.
Two main techniques are used for the TDC architectures. The first one makes use of a voltage ramp started or stopped by the digital pulse. The obtained voltage is converted into digital data using an Analog to Digital Converter (ADC). The timing resolution of such a system is excellent (5 ps rms). But this technique is limited by its large dead time which can be unacceptable for the future high rate experiments. Another popular technique associates a coarse measurement performed by a digital counter with a fine measurement (interpolation) using Delay Line Loop. Such a system can integrate several (8-16) channels on an FPGA or an ASIC. The most advanced DLL-based TDC ASIC exhibits a timing resolution of 25 ps, but only after a careful calibration.
It should be noticed that the overall timing resolution is given by the quadratic sum of the discriminator and of the TDC.
In the meantime, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit achieving a timing resolution far better than the sampling frequency. For example, 100ps rms resolution has been reported for a signal sampled at only 100MHz.
Digitization systems have followed the progress of commercial ADCs, which currently offer a rate of 500 MHz over 12 bits. Their main drawbacks are the huge output data rate and power consumption. Their packaging, cooling, and tricky clock requirements also makes them very hard to implement. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption.
The new USB-WaveCatcher board has been designed to provide high performances over a short time window. It houses on a small surface two 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAM chip, an analog circular memory of 256 cells per channel. Its innovative matrix design permits reaching these performances, yet in a cheap pure CMOS 0.35µm technology, while consuming only 300 mW.
Raw sampling precision is as good as 15ps rms. In an embodiment where the clock is directly sent to the SAM chip, thus limiting the usable sampling frequency to 3.2GHz, and after a calibration of the fixed pattern time distribution, a reproducible time precision of a few ps has been demonstrated.
The board also offers various functionalities. Its input offset is tunable over a range of 2 V. It can be triggered either internally or externally and several boards can easily be synchronized. Trigger rates counters are implemented. Both channels can also be used for reflectometry thanks to their internal pulser. The precision obtained for cable length measurements is as good as 2mm. Charge measurement mode is also provided, through integrating on the fly over a programmable time window the signal coming for instance from photo-multipliers. Power consumption is only 2.5 W which permits powering with the sole USB. Signal connectors can be BNC, SMA or LEMO.
The board houses a USB 12 Mbits/s interface permitting a dual-channel readout speed of 500 events/s. Faster readout modes are also available. In charge measurement mode, the sustained trigger rate can reach a few tens kHz. A 480Mbits/s version will soon be available.
Various evolutions of the SAM chip are under study, targeting either higher precision time measurements or longer time window.
The USB-WaveCatcher can thus replace oscilloscopes for a much lower cost in most high-precision short-window applications. Moreover, it opens new doors into the domain of very high precision time measurements.