Speaker
Mr
Vincent Pierre Delord
(ISIMA-Clermont Ferrand)
Description
The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid.
The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. This means speeding up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or technologies and might also need new networking protocols: a customized TCP or proprietary solutions.
A test module is being presented, which integrates in the existing LHCb infrastructure. It is a 10-Gigabit traffic generator, flexible enough to generate LHCb's raw data packets using dummy data or simulated data.
These data are seen as real data coming from sub-detectors by the DAQ. The implementation is based on an FPGA using 10 Gigabit Ethernet interface. This module is integrated in the experiment control system.
The architecture, implementation, and performance results of the solution will be presented.
Author
Mr
Vincent Pierre Delord
(ISIMA-Clermont Ferrand)
Co-authors
Mr
Jean-Christophe Garnier
(CERN LHCb)
Niko Neufeld
(CERN LHCb)