Mr
Hugo Franca Santos
(CERN)
24/09/2009, 16:15
ASIC's
Poster
This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage....
Mr
Yunan FU
(DRS-IPHC, University of Strasbourg, CRNS-IN2P3)
24/09/2009, 16:15
ASIC's
Poster
CMOS Monolithic Active Pixel Sensors (MAPS) combined with 3D Integrated Technologies (3DIT) offer new opportunities to meet the challenging requirements of the next generation pixel technologies. This paper presents a 3D CMOS pixel sensor design adapted to the innermost layer of the ILC vertex detector. It contains a matrix of 96x256 pixels; each integrating, in a 12µm pitch, a sensing...
Federico Alessio
(CERN)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on...
Mr
Fatah Rarbi
(IN2P3 / LPSC Grenoble)
24/09/2009, 16:15
ASIC's
Poster
The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 32 analog channels through one analog to digital converter. A...
Mr
Piotr Jurga
(CERN)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The Timing Trigger and Control (TTC) system distributes timing signals from the LHC Radio Frequency (RF) source to the four experiments. A copy of these signals is also transmitted to a monitoring system, installed in the Control Center in Prevessin, which provides continuous measurement of parameters such as Bunch Clock jitter and frequency, Orbit period in BC counts, transmission delay over...
Mr
Felix Müller
(Kirchhoff Institute for Physics, University of Heidelberg)
24/09/2009, 16:15
Production, testing and reliability
Poster
A scalable multi-channel analogue signal generator is presented. It uses a commercial low-cost graphics card with multiple outputs in a standard PC as signal source. Each color signal serves as independent channel to generate an analogue signal. A custom-built external PCB was developed to adjust the graphics card output voltage levels for a specific task, which needed differential signals....
Gianmaria Collazuol
(INFN Sezione di Pisa (INFN))
24/09/2009, 16:15
Trigger
Poster
We describe a pilot project for the use of GPUs in an online triggering
application at the CERN NA62 experiment, and the results of the first
field tests together with a prototype data acquisition system.
Mr
Vincent Pierre Delord
(ISIMA-Clermont Ferrand)
24/09/2009, 16:15
Optoelectronics and Links
Poster
The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid.
The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. ...
Dr
Alexander A. Grillo
(Santa Cruz Institute for Particle Physics, University of California, Santa Cruz)
24/09/2009, 16:15
ASIC's
Poster
The upgrade of the ATLAS detector for the high luminosity upgrade of the LHC will require a rebuild of the Inner Detector as well as replacement of the readout electronics of the Liquid Argon Calorimeter and other detector components. We proposed some time ago to study silicon germanium (SiGe) BiCMOS technologies as a possible choice for the required silicon microstrip and calorimeter...
Mr
Tim Armbruster
(Heidelberg University)
24/09/2009, 16:15
ASIC's
Poster
The development of front-end electronics for the planned CBM experiment at FAIR/GSI is in full progress. For the charge readout of the various subdetectors a new self triggered amplification and digitalization chip is being designed and tested. The chip will have 32-64 channels each containing a low power/low noise preamplifier/shaper front-end, an 8-9 Bit ADC and a digital post-processing...
Mr
Abdelkader HIMMI
(DRS-IPHC, University of Strasbourg, CNRS-IN2P3)
24/09/2009, 16:15
ASIC's
Poster
The EUDET-JRA1 beam telescope and the STAR vertex detector upgrade will be equipped with CMOS pixel sensors allowing to provide high density tracking adapted to intense particle beams. The EUDET sensor Mimosa26, is designed and fabricated in a CMOS-0.35µm Opto process. Its architecture is based on a matrix of 1152x576 pixels, 1152 column-level analogue-to-digital conversion by discriminators...
Mr
Eric Delagnes
(CEA/Irfu)
24/09/2009, 16:15
ASIC's
Poster
The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan, for which a near detector complex (ND280), used to characterize the beam, will be built 280m from the target in the off-axis direction of the neutrino beam produced using the 50 GeV proton synchrotron of J-PARC (Japan Proton Accelerator Research Complex). The central part of the ND280 is a...
Dag Toppe Larsen
(University of Bergen)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
ALICE is a dedicated heavy-ion experiment at CERN LHC. It aims to
reproduce the state of matter shortly after the Big Bang, i.e. the
quark-gluon plasma. Each lead-lead collision will produce the order of
ten thousand new particles. Detailed study of the event requires precise
measurements of the particle tracks. An 95m3 Time Projection Chamber
(TPC) with more than 500 000 read-out pads...
Dr
Raffaele Giordano
(Universita' di Napoli Federico II and INFN, Napoli)
24/09/2009, 16:15
Optoelectronics and Links
Poster
The ATLAS Level-1 barrel muon trigger is built as a synchronous pipeline and includes some high-speed serial links in order to transfer data from the detector to the counting room. The links are based on the GLink chip-set, which transfers data
with a fixed and deterministic latency. Despite its unique timing features, the production discontinued and no compatible off-the-shelf chip-sets are...
Mr
Michal Bochenek
(CERN)
24/09/2009, 16:15
ASIC's
Poster
After the LHC luminosity upgrade the number of readout channels in the ATLAS Semiconductor Tracker will be increased. Therefore a new solution for powering the readout electronics has to be found.
The two main approaches for power distribution are under development, the serial powering of a chain of modules and the parallel powering with DC-DC conversion. In both cases...
Mr
François WICEK
(LAL IN2P3 CNRS)
24/09/2009, 16:15
ASIC's
Poster
The ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%.
The architecture is based on a double correlated sampling. 2 methods have been investigated: differential output Dual Slope Integrator which has been chosen to be the LSST baseline and...
Dr
Peter Vankov
(University of Liverpool)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The ATLAS experiment at the CERN Large Hadron Collider (LHC) has started taking data last autumn with the inauguration of the LHC. The SemiConductor Tracker (SCT) is the key precision tracking device in ATLAS, made up from silicon micro-strip detectors.
The completed SCT has been installed inside ATLAS. Since then the detector was operated for many months under realistic conditions....
Mr
Matt Warren
(UCL)
24/09/2009, 16:15
ASIC's
Poster
The ATLAS Tracker Upgrade project is developing large modules of up to two hybrids each. Each hybrid comprises two columns of ABCN-25 readout ASICs, each with a data rate twice the bunch-clock. A hybrid readout link thus handles two streams at quadruple the bunch-clock rate. To allow hybrids to operate at different potentials (as required by serial-powering), control signals make use of a...
Mr
Sergio Silva
(CERN)
24/09/2009, 16:15
Optoelectronics and Links
Poster
In the context of the versatile link project, a set of semiconductor lasers were studied and modeled aiming at the optimization of the laser driver circuit. High frequency measurements of the laser diode devices in terms of reflected and transmission characteristics were made and used to support the development of a model that can be applied to study their input impedance characteristics and...
Andre Konrad Kruth
(Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany)
24/09/2009, 16:15
ASIC's
Poster
FE‐I4 is the 130nm ATLAS pixel IC currently under development for upgraded LHC luminosities. FE‐I4 is based on a low‐power analog pixel array and digital architecture concepts tuned for higher hit rates. An integrated PLL has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40MHz bunch crossing reference. This block is designed for low‐power,...
Mr
Alexey Kozyrev
(BINP)
24/09/2009, 16:15
Trigger
Poster
The cryogenic magnetic detector CMD-3 developed for experiments on elektron-pozitronnom collider VEPP-2000 is under construction at Budker Institute of Nuclear Physics now. This paper describes the modules which are forming an infrastructure and datapath of the First Level Trigger (FLT) of CMD-3. There are few types of modules specially developed for detector subsystems. These modules are...
Mikhail Matveev
(Rice University)
24/09/2009, 16:15
Optoelectronics and Links
Poster
The Endcap Muon (EMU) Cathode Strip Chamber (CSC) sub-detector at the CMS experiment at CERN has been fully installed and operational since summer of 2008. The system of 180 optical links connects the middle and upper levels of the CSC Level 1 Trigger chain. Design and commissioning of all optical links presents several challenges, including reliable clock distribution, link...
Dr
Fernando Arteche
(Instituto Tecnológico de Aragón)
24/09/2009, 16:15
Power, grounding and shielding
Poster
This paper presents a detailed and comparative analysis from the electromagnetic compatibility point of view of the proposed power distributions for the SLHC tracker up-grade. The main idea is to identify and quantify the noise sources, noise distribution at the system level and the sensitive areas in the front-end electronics corresponding to both proposed topologies: The DC-DC converter...
Mr
Jan Scheirich
(Charles University in Prague, Faculty of Mathematics and Physics)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The Mini-matrix readout system is being developing for measuring characteristics of a small (3.5 x 3.5 mm) prototype of a DEPleted Field Effect Transistor (DEPFET) sensor for particle detection. The small sensor will have 8 x 6 active pixels allowing studies of the DEPFET structure behaving and processes during sensor operation. The Mini-matrix readout setup should allow us to make a precision...
Mr
Szymon Kulis
(Fac. of Phys. & Applied Comp. Sci.-AGH Univ. of Science & Techno)
24/09/2009, 16:15
ASIC's
Poster
The design and preliminary measurement results of a prototype 10 bit pipline ADC for the Luminosity Detector (LumiCal) at the International Linear Collider (ILC) are presented. The motivation for the chosen architecture is presented and followed by the description of the core blocks. The prototype was fabricated in 0.35 um CMOS technology. The preliminary measurements of static (INL, DNL) and...
Mr
Wim Beaumont
(Universiteit Antwerpen)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The CMS CASTOR detector is a small calorimeter located at 14.3 meters from the interaction point behind the HF detector. The CASTOR project was only approved mid of 2007. Cherenkov radiation in a sampling structure is used to measure the energy as the HF does. Logically one would use the same readout hardware as used for HF. But also other architectures were considered. Given the...
Georgi Leshev
(Labor fur Hochenergiephysik)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The challenging constraints on the design of the Electromagnetic Calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment, such as rigorous temperature and voltage stability, imposed the development of a complex Detector Control System (DCS). In this paper the final layout and functionality of the CMS ECAL DCS are presented and the operational experience during the detector's...
Mr
Claudio Bortolin
(Universita degli Studi di Udine)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The Silicon Pixel Detector (SPD) is the section of the ALICE Inner
Tracking System closest to the interaction point. In order to operate the detector in a safe way, a control system was developed in the framework of PVSS which allows monitoring a large number of parameters such as temperatures, currents, etc.
The control system of the SPD implements interlock features to protect the detector...
Mr
Datao Gong
(Southern Methodist Univeristy)
24/09/2009, 16:15
ASIC's
Poster
Radiation tolerant, high speed and low power serializer ASIC is used for optical digital data links systems in particle physics. Based on a commercial 0.25 μm silicon-on-sapphire CMOS technology, we designed a 16:1 serializer with a 5 Gbps serial data rate. We present the design details and post layout simulation results. This ASIC will be submitted for fabrication in August 2009. A shared PLL...
Mr
Sebastian Schopferer
(University of Freiburg)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The GANDALF transient recorder with a resolution of 12bit@1Gsps has been developed to sample analog signal pulses with fast rising edges (3ns) and large dynamic ranges at the COMPASS experiment. Signals are digitized and processed by fast algorithms to extract pulse arrival times and amplitudes in real-time and to generate experiment trigger signals.
With 8 analog channels, deep memories and...
Dr
Sandro Bonacini
(CERN)
24/09/2009, 16:15
Optoelectronics and Links
Poster
the e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The e-link is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable Low-Voltage Signaling (SLVS)...
Mr
Jan Buytaert
(CERN)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The LHCb experiment plans to upgrade the entire detector and increase its running luminosity by a factor 10, by 2015/2016. This will require a full scale replacement of the front end electronics, to enable all detector information to be read out at 40 MHz and combined in the first level trigger executed on a PC-farm. In addition, the parts of the detector which suffer from radiation damage...
Prof.
Marco Meschini
(Istituto Nazionale di Fisica Nucleare, Firenze, Italy)
24/09/2009, 16:15
Optoelectronics and Links
Poster
We demonstrate the feasibility of 10.7 Gb/s error-free (BER < 1e-12) optical transmission on distances up to 2 km using a recently developed ultra-low-voltage commercial electro-optic modulator (EOM) that is driven by 0.6 Vpp and with an optical input power of 1 mW. Thus, the modulator could be driven directly from the detectors’ board signals without the need of any further amplification...
Mr
Stefan Haas
(CERN)
24/09/2009, 16:15
Trigger
Poster
The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to...
Ms
Annie Xiang
(Southern Methodist University)
24/09/2009, 16:15
Optoelectronics and Links
Poster
Serial optical data transmission provides a solution to High Energy Physics experiments' readout systems with high bandwidth, low power, low mass and small footprint. It will commonly be used in detector upgrades for the SLHC. In the meanwhile, commercial FPGAs with embedded multi-gigabit transceivers have become accessible. We develop a test bench with such a device at its core to verify link...
Fernando Arteche
(Instituto Tecnologico Aragon - Saragoza - Spain)
24/09/2009, 16:15
Power, grounding and shielding
Poster
The identification of the coupling mechanisms between noise sources and sensitive areas of the front-end electronics (FEE) in the previous CMS tracker sub-system is critical to optimize the design of integrated circuits and hybrids for the proposed SLHC Silicon Strip Tracker systems. This paper presents a validated model of the noise sensitivity of the Silicon Strip Detector-FEE of the CMS...
Mohsine Menouni
(CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)
24/09/2009, 16:15
ASIC's
Poster
The design of the front-end (FE) pixel electronics requires high speed, low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the...
Dr
Valeria Sipala
(I.N.F.N. Catania)
24/09/2009, 16:15
Production, testing and reliability
Poster
A proposal for a system to capture signals in the Optical Module of an underwater neutrino telescope is described, with focus on power consumption and dynamics considerations. All considerations regarding the signals and their acquisition are made starting from the most general hypothesis possible, so that they will be valid for any underwater Cherenkov neutrino telescope.
A front-end board,...
Dr
Thomas NOULIS
(Electronics Lab. , Physics Dept., Aristotle Univ. of Thessaloniki, 54124 Thessaloniki Greece)
24/09/2009, 16:15
ASIC's
Poster
Alternative current mode charge sensitive amplifier (CSA) topology and related methodology for use as pre-amplification block in radiation detection read out front end IC systems is proposed. It is based on the use of a current conveyor architecture providing advantageous noise performance characteristics in comparison to the typically used CSA folded caccode structure. In the proposed...
Mr
Damien Thienpont
(IN2P3/LAL)
24/09/2009, 16:15
ASIC's
Poster
The OMEGAPIX circuit is the first front end prototype ASIC designed at LAL (Orsay) using 3D technology for the ATLAS upgrade SLHC pixel project. This work has been done inside a new international consortium for development of Vertical Integrated Technologies for Electronics and Silicon SEnsors (VITESSE), which has gathered, not only 3 IN2P3 (France) institutes, but also Fermilab (USA) and...
Dr
Isabelle Valin
(DRS-IPHC, University of Strasbourg, CNRS-IN2P3)
24/09/2009, 16:15
ASIC's
Poster
In a detector system, clock distribution to sensors must be controlled at a level allowing proper sensors synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), it has been proposed to distribute a low frequency clock at 10 MHz which will be multiplied in each sensor by a PLL to 160 MHz. A PLL was designed for low...
Dr
Jean-Francois Genat
(University of Chicago)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
Micro-Channel Plates anodes are coupled to fast transmission lines in order to reduce the number of electronics readout channels, and provide two-dimensions position measurements using centroids and two-ends delay timing. Tests using a laser and waveformanalysis have shown that resolutions of a few hundreds of microns along thetransmission line can be reached. This technique is planned to be...
Mr
Stéphane Callier
(Laboratoire de l'Accélérateur Linéaire)
24/09/2009, 16:15
ASIC's
Poster
The OMEGA group at LAL has designed 3 chips for ILC calorimeters: one analog (SPIROC) and one digital (HARDROC) for the hadronic one and also one for the electromagnetic one (SKIROC). The readout and the management of these different chips will be explained.
To minimize the lines between the ASICs and the DAQ, the readout is made thanks to 2 lines which are common for all the chips: Data and...
Mr
Sergio Díez
(Instituto de Microelectrónica de Barcelona - Centro Nacional de Microelectronica IMB-CNM (CSIC), Spain)
24/09/2009, 16:15
Radiation tolerant components and systems
Poster
We present in this paper radiation hardness studies on devices of the 130 nm 8WL Silicon Germanium (SiGe) BiCMOS technology from IBM. This technology has been proposed as one of the candidates for the Front-End (FE) readout chip of the upgraded Inner Detector (ID) and the Liquid Argon Calorimeter (LAr) of the ATLAS Upgrade experiment. Gamma, neutron and proton radiation experiments have been...
Dr
Markus Friedl
(HEPHY Vienna)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
A prototype readout system has been developed for the future Super-
Belle Silicon Vertex Detector at the Super-KEK-B factory in Tsukuba,
Japan. It will receive raw data from double-sided sensors with a total
of approximately 250,000 strips read out by APV25 chips at a trigger
rate of up to 30kHz and perform strip reordering, pedestal subtraction,
a two-pass common mode correction and zero...
Mr
Stépahne Callier
(Laboratoire de l'Accélérateur Linéaire)
24/09/2009, 16:15
ASIC's
Poster
The SPIROC chip is a dedicated very front-end electronics for an ILC technical prototype hadronic calorimeter with Silicon Photomultiplier (or MPPC) readout. This ASIC is due to equip a 2,000-channel demonstrator in 2009. The SPIROC chip is the successor of the ILC_SiPM ASIC presently used for the ILC AHCAL physics prototype incorporating additional features like autotriggering, pipelines,...
Vasilii Kushpil
(Academy of Sciences of the Czech Republic (ASCR))
24/09/2009, 16:15
Production, testing and reliability
Poster
This paper describes a new electronics module for converting a parallel data flow to a serial stream in the USB 2.0 High Speed protocol. The system provides a connection between a PC USB port and a parallel interface of the DAQ board, which is used for investigation of performance of Active Pixel Sensors (APS) prototypes. The DAQ readout software supports Win XX OS and Linux OS. GUI examples...
Dr
Thijs Wijnands
(CERN)
24/09/2009, 16:15
Radiation tolerant components and systems
Poster
Based on the principle of the RADMON on line radiation monitoring system for the LHC, a new type of low cost, battery powered radiation monitors has been designed that do not need external cabling. In this paper we will outline the hardware design, summarise on the radiation tolerant components and tests and describe the associated usb interace and labview software. First operational data from...
Mr
Babak Abi
(Oklahoma State University)
24/09/2009, 16:15
Radiation tolerant components and systems
Poster
We study the radiation hardness of PiN diodes which are part of the optical link. These components were irradiated by 200 MeV protons up to 8.2 x 10exp(15) 1-MeV neq/cm2 ( 84 MRad). The responsivity of PiN diodes are measured as a function of the radiation dose to estimate life time reliability of diodes.
Mr
Nicolai Schroer
(Ruprecht Karls Universitaet Heidelberg)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
About 600 custom-built ReadOut Buffer INput (ROBIN) PCI boards are used in the Data-Collection
of the ATLAS experiment at CERN. In the standard setup requests and event data are passed via the
PCI interfaces. The performance meets the requirements, but may need to be enhanced for more
demanding use cases. Modifications in the software and firmware of the ROBINs have made it
possible to...
Mrs
Jennifer Boek
(Bergische Universitaet Wuppertal)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
For the sLHC upgrade a new ATLAS Pixel Detector is planned, which will require a completely new Control System.
The requirements, a first concept and a layout will be presented. We will focus on a control chip which necessarily has to be implemented in the new Detector Control System. A setup of discrete components has been built up to investigate and verify the chip's requirements.
First...
Mr
Tiankuan Liu
(Southern Methodist University)
24/09/2009, 16:15
ASIC's
Poster
Detector front-end readout upgrades for the ATLAS Liquid Argon Calorimeter call for radiation tolerant, high speed, and low power optical digital data links. In the development for a high speed, low power serializer ASIC, we have designed an LC-based phase locked loop (PLL) using a commercial 0.25-µm Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that we can...
Mr
Guido Volpi
(INFN, Sezione di Pisa-Unknown-Unknown)
24/09/2009, 16:15
Trigger
Poster
Hadron collider experiments search for extremely rare processes hidden in much larger background levels. Only a tiny fraction of the produced collisions can be stored on tape and an enormous real-time data reduction is needed. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise...
Dr
Alessandro Gabrielli
(CERN EP-MIC - Physics Department & INFN Bologna)
24/09/2009, 16:15
ASIC's
Poster
This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a...
Dr
Michele Caselle
(CERN - Università Degli Studi di Bari)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The SPD forms the two innermost layers of the ALICE experiment. It is equipped with a total of 120 modules (half-staves) with a total number of 9.8 x 106 readout channels. Each half-stave is connected via three optical links to the off-detector electronics made of FPGA based VME readout cards (Routers). The Routers and their mezzanine cards provide the zero-suppression, data formatting and...
Ms
Costanza Cavicchioli
(CERN)
24/09/2009, 16:15
Trigger
Poster
The ALICE Silicon Pixel Detector (SPD) constitutes the two innermost layers of the ALICE experiment. It consists of 1200 pixel chips with a total of ~107 channels with a pixel size of 50x425 μm2.
Each pixel chip transmits a Fast-Or signal upon registration of at least one pixel hit. These signals are extracted every 100 ns and processed by the Pixel Trigger (PIT) system. A signal is then...
Mrs
Serena Mattiazzo
(Dipartim. di Fisica Galileo Galilei-Universita degli Studi di Pa)
24/09/2009, 16:15
Radiation tolerant components and systems
Poster
A monolithic pixel detector in deep-submicron Silicon On Insulator (SOI) technology has been developed and characterized. This summary presents the first assessments of the effect of ionizing radiation as regards the total dose damage on single transistors in the technology used for the development of the first prototype chip. This work shows the decisive effect of the substrate bias condition...
Jens Dopke
(University of Wuppertal)
24/09/2009, 16:15
Optoelectronics and Links
Poster
The first upgrade for the ATLAS pixel detector will be an additional layer, which is called IBL (Insert-able B-Layer). To readout this new layer having new electronics assembled an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth and also compatible with the existing system to be integrated into it. The talk will...
Ms
Agnes Rudert
(Atlas HEC)
24/09/2009, 16:15
Radiation tolerant components and systems
Poster
The signal amplification and summation electronics of the ATLAS Hadronic End-cap Calorimeter
(HEC) is operated at the circumference of the HEC calorimeters inside the cryostats in liquid argon.
The present electronics is designed to operate at irradiation levels expected for the LHC. For
operation at the sLHC the irradiation levels are expected to be a factor 10 higher, therefore a new...
Mr
Peter Phillips
(Particle Physics)
24/09/2009, 16:15
Systems, installation and commissioning
Poster
The ABCN-25 chip was fabricated in 2008 in the IBM 0.25 micron CMOS process. One wafer was immediately diced to make chips available for evaluation with test PCBs and hybrids, programmes which are reported separately. Early indications based on the diced wafer suggested a percentage yield in the high nineties, however the community decided to screen the remaining wafers such that faulty die...
Dr
Ozgur Cobanoglu
(CERN, PH-ESE-ME)
24/09/2009, 16:15
ASIC's
Poster
This paper describes the data serializer of the GigaBit Transceiver (GBT) which has been under development for the LHC upgrade (SLHC). The circuit operates at 4.8 Gb/s and is implemented in a commercial 130 nm CMOS technology. The serializer occupies an area of 0.6 mm² and its power consumption is 300 mW. The paper focuses on the techniques used to achieve radiation tolerance and on the...
