21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

Low power discriminator for ATLAS pixel chip

24 Sept 2009, 16:15
2h 15m
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Poster ASIC's POSTERS SESSION

Speaker

Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)

Description

The design of the front-end (FE) pixel electronics requires high speed, low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is greatly reduced.

Summary

A pixel FE pixel chip is developed in a 130nm CMOS technology for the B-layer replacement. The chip contains around ~27,000 pixels of 50μm×250μm each. The pixel contains a fast charge preamplifier, a second stage amplifier, a discriminator and a logic bloc to transfer the hit information to the chip periphery.
The current pixel design uses a continuous biased discriminator where the bias current is defined in order to reach the required speed and to minimise the time walk. This allows assigning the hits to their corresponding bunch numbers with high probability. In the main analog pixel architecture flavour studied, the discriminator power consumption can reach 20% of the total pixel power budget.
Since the average counting rate for one pixel is low, it is possible to greatly reduce the power consumption of the pixel if the discriminator is biased only when a hit is present.
This paper proposes an efficient way to design very low power discriminators for pixel detectors. Two different architectures based on the dynamic biasing principle are proposed.
In the first one, an input differential stage controls the bias of the main comparator stage. The input voltage signal is converted to a current signal used to bias the second stage after applying a multiplicative factor.
The second architecture uses two stages. An auxiliary comparator with a low threshold value powers up selectively the main comparator stage.
A prototype test chip has been designed as an array of ~300 pixels. Different discriminator architectures were implemented in this design. The chip is submitted for fabrication in 130 nm CMOS technology. We will be able to compare power consumption, noise and dispersion performances, as well as timing and crosstalk performances for the implemented architectures.

Primary author

Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)

Co-authors

Abderrezak Mekkaoui (LBNL - Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, United States of America) Alexandre Rozanov (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France) Andre Kruth (Bonn - Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany) Dario Gnani (LBNL - Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, United States of America) David Arutinov (Bonn - Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany) David Elledge (LBNL - Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, United States of America) Denis Fougeron (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France) Fabrice Gensolen (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France) Giovanni Darbo (Genova - INFN Genova via Dodecaneso 33, IT - 16146 Genova, Italy) Jan David Schipper (Nikhef - Nikhef, National Institute for Subatomic Physics, Kruislaan 409, 1098 SJ Amsterdam, The Netherlands) Marlon Barbero (Bonn - Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany) Maurice Garcia-Sciveres (LBNL - Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, United States of America) Michael Karagounis (Bonn - Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany) Roberto Beccherle (Genova - INFN Genova via Dodecaneso 33, IT - 16146 Genova, Italy) Ruud Kluit (Nikhef - Nikhef, National Institute for Subatomic Physics, Kruislaan 409, 1098 SJ Amsterdam, The Netherlands) Sourabh Dube (LBNL - Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, United States of America) Tomasz Hemperek (Bonn - Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany) Vladimir Gromov (Nikhef - Nikhef, National Institute for Subatomic Physics, Kruislaan 409, 1098 SJ Amsterdam, The Netherlands)

Presentation materials