21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

DEPFET Mini-matrix Readout System

24 Sept 2009, 16:15
2h 15m
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Poster Systems, installation and commissioning POSTERS SESSION

Speaker

Mr Jan Scheirich (Charles University in Prague, Faculty of Mathematics and Physics)

Description

The Mini-matrix readout system is being developing for measuring characteristics of a small (3.5 x 3.5 mm) prototype of a DEPleted Field Effect Transistor (DEPFET) sensor for particle detection. The small sensor will have 8 x 6 active pixels allowing studies of the DEPFET structure behaving and processes during sensor operation. The Mini-matrix readout setup should allow us to make a precision collected charge measurement in each pixel with low noise, charge shearing among multiple pixels, clustering, charge-loss measurement, find optimal voltage values and timing of driving signals and should allow us to make a computer post-analysis as a correlated sampling, averaging, etc. The system is made of a commercial and custom-made blocks as a PC with an 8-channel 14-bit 125 Msps PCI data acquisition card, FPGA control card, current readout and switching circuit and differential to single-ended converter. The custom-made current readout circuit is made of 8 low noise trans-impedance readout amplifiers and the switching circuit contains 12 individual analog switches that are necessary to control the Gate and Clear electrodes of the DEPFET Mini-matrix sensor. The measuring system will be controlled and configured by PC. Total input noise should be below 20 e- (electrons). All 8 channels will be digitalized by 14-bit ADCs with 125 Msps for each channel in parallel with frame readout time 20 s. The switching circuit will have possibility of gate voltages timing with resolution of 10 ns and allows gate signals overlapping. Subtracting voltage for the pedestal current subtraction will be digitally reconfigurable. The system concept is simple, based on the previous single pixel measuring setups and should provide fast realization and precise results.

Primary author

Mr Jan Scheirich (Charles University in Prague, Faculty of Mathematics and Physics)

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