21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

Commissioning and performance of the Preshower off-detector readout electronics in the CMS experiment

22 Sept 2009, 12:15
25m
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Oral Systems, installation and commissioning Parallel session B1 - Systems, Installation and Commissioning

Speaker

Dr Paschalis Vichoudis (CERN)

Description

The CMS Preshower is a fine grain detector that comprises 4288 silicon sensors, each containing 32 strips. The raw data are transferred from the detector to the counting room via 1208 optical fibres producing a total data flow of ~72GB/s. For their readout, 40 multi-FPGA 9U VME readout boards are used. This article is focused on the commissioning of the VME readout system using two tools: a custom connectivity test system based on FPGA embedded logic analyzers read out through JTAG; an FPGA-based system that emulates the data-traffic from the detector. Additionally, the performance of the VME readout system in the CMS experiment, including the 2009 CRAFT run (Cosmic ray at Four Tesla), is discussed.

Summary

The CMS Preshower is a fine grain detector that comprises 4288 silicon sensors, each containing 32 strips. The raw data are transferred from the detector to the counting room via 1208 optical fibres producing a total data flow of ~72GB/s. For their readout, 40 multi-FPGA 9U VME readout boards known as "ESDCC" have been produced. The ESDCCs also perform significant data reduction since the the total available downstream bandwidth of the central DAQ system is ~8GB/s. The required level of data reduction is feasible since the maximum occupancy is relatively low in the Preshower - an average of about 2%. This article is focused on the commissioning of the VME readout system as well as its performance in the CMS experiment.

The first stage of commissioning of the system was the connectivity test of the major FPGA-based components comprising the ESDCC: up to 3 multi-channel optical receiving plug-in modules (known as the "optoRx") and their 9U VME "host board". The tool used to verify the connections is a custom connectivity test system based on FPGA embedded logic analyzers. The concept of the testing method is the following: In order to verify one connection line, the line must be toggled from the one end and read/verified on the other end. To do so, one or more FPGAs of the unit under test are generating certain patterns that are received by other FPGAs of the same unit. In case of open connections (e.g. from an FPGA to a connector), special PCBs are attached to the connectors and redirect the signals to other FPGA IO lines. The patterns are triggering the embedded logic analyzers in the receiving end, being recorded and readout through JTAG. A LabVIEW application that compares the expected results with the ones received from the unit under test as well as presents the pin locations of the faulty connections has also been developed.

By combining existing modules, a second FPGA-based test system known as the "ESDTE" (Preshower Data Traffic Emulator) has been developed. This serves as the primary ESDCC evaluation tool in the laboratory. As its name suggests, the ESDTE emulates the front-end of the Preshower, providing user-programmable data patterns combined (or not) with real previously recorded data from the detector. The ESDCC can thus be commissioned without the need for the real detector hardware as a data source. In addition, the ESDTE is able to generate rare (but possible) error conditions that are not easily reproducible with the real detector, such as synchronization problems, missing or spurious events, corrupted data packets etc. Flexible software tools have been developed to accompany this hardware, enabling easy control of both the ESDTE and ESDCC (C++ programs) as well as the subsequent data analysis (based on MatLab).

The last part of the article is focused in the performance of the ESDCC in realistic conditions, both during detector assembly and in-situ in CMS, including the 2009 "CRAFT" run (Cosmic Rays At Four Tesla). The maximum event rates with and without data reduction, the data reduction factor achieved, synchronicity issues, time needed for the loading of operating parameters, time needed for the FPGA configuration through VME, operating temperatures etc. are all discussed.

Author

Co-authors

Chia-Ming Kuo (National Central university, Taipei, Taiwan) Dr David Barney (CERN) Mr Gueorgui Antchev (CERN & INRNE-BAS, Sofia, Bulgaria) Mr Juan Sebastian Rodriguez Estupinan (Universidad de los Andes, Bogotá, Colombia) Dr Kai-Feng Chen (NTU, Taipei, Taiwan) Dr Rong-Shyang Lu (NTU, Taipei, Taiwan) Mr Ruy Sebastian Bonilla Osorio (Universidad de los Andes, Bogotá, Colombia) Mr Serge Reynaud (CERN) Mr Vaios Patras (University Of Ioannina, Ioannina, Greece) Dr Wojciech Bialas (CERN)

Presentation materials