TWEPP-09 Topical Workshop on Electronics for Particle Physics

Low Power Analog Design in Scaled CMOS Technologies

22 Sept 2009, 14:15

45m

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Oral ASIC's Plenary Session 2 - Low Power Analog Design Techniques

Speaker

Andrea Baschirotto (University of Milan-Bicocca)

Description

The running CMOS technology scaling has a big impact in the design of analog circuits. Since scaled technologies offer big advantages to digital parts (reduce space, lower power consumption, etc...), complex mixed-signal systems are typically developed in the smallest minimum-gate-length technology. However these advantages for the digital part in a scaled technology correspond to a big penalty in the analog design. Typical problems are due to the lower output impedance, to the lower available output swing and to the lower distance from VDD to VTH (VDD scales faster than VTH). Analog designers have then to develop new solutions for achieving in scaled technologies the same performance previously achieved in "older" technologies. In this talk these problems will be addressed for the cases of basic building blocks. The discussion will then move to their effects on complex systems showing the possible solutions in 90nm/65nm.

Presentation materials

Slides

TWEPP09_Baschirotto_Full.pdf

TWEPP09_Baschirotto_Pres.pdf