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Description
Summary
This paper concerns the 100 MSamples/s ADC developed for the IN2P3 INNOTEP project.
The architecture chosen is a 4 stages pipeline. Each stage is designed with 2.5bits to get an overall resolution of 8 bits.
This architecture needs 6 comparators per stage (for the 2.5bits system), two track and holds, a 3 bits DAC and an amplifier with a good accuracy and a gain of 4.
Each design is fully differential and open loop to minimize the kick back noise and the stability problems.
Two versions are described, the first release which uses one track and hold per stage and has a conversion time of 20ns, and the last release with two track and holds per stage and conversion time of 40ns. The conversion time has increased, but it is not a critical point because the aperture size latency is the same, 10ns in each version. The second release offers better results than the first in conversion precision.
In each version, a part of the stages uses current structure, to limit the kick back noise
and the charge injections in the 3 bits DAC, and to offer more precision in the open loop gain amplification and reference subtraction.
The choice of handling the signal in current mode instead of in voltage for the comparison and subtraction stage as well as in the DAC is discussed, and simulation results are given. The choice to use two track and holds instead of one is discussed too, with comparisons using simulation results.
Simulations to verify the robustness to the process/matching variations were made.
The Layout is realized for each version, the first version was sent on June 2008 and the second on March 2009. Parasitic simulations were made and are discussed, and the two chips will be tested for the workshop. The test’s results will be described, such as measurements of static performances, yield results.
Comparisons between test’s results and parasitic simulations will be made.
