Conveners
Parallel Session B3 - Packaging and Interconnects
- Ray Yarema (FNAL)
Parallel Session B3 - Packaging and Interconnects
- Jorgen Christiansen (CERN)
40.
Construction and Performance of a Double-Sided Silicon Detector Module using the Origami Concept
Mr
Christian Irmler
(HEPHY Vienna)
23/09/2009, 09:45
Packaging and interconnects
Oral
The APV25 front-end chip with short shaping time will be used in the Super-Belle Silicon Vertex Detector (SVD) in order to achive low occupancy. Since fast amplifiers are more susceptible to noise caused by their capacitive input load, they
have to be placed as close to the sensor as possible. On the other hand, material budget inside the active volume has to be kept low in order to reduce...
Dr
Anna Macchiolo
(Max-Planck-Institut fuer Physik)
23/09/2009, 10:10
Packaging and interconnects
Oral
We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting vertical integration technologies developed at the Fraunhofer Institute IZM-Munich. A new Solid-Liquid-InterDiffusion technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the...
Mr
Ashley Greenall
(Department of Physics)
23/09/2009, 11:00
Packaging and interconnects
Oral
We will present the development of prototype flex hybrids and modules for the short strip layers of the ATLAS inner detector upgrade. The hybrid utilises the ABCN-25 front end readout chip, which has been optimised for the short 2.5cm strip sensor topology. The design and production choices for a high yield, low cost reliable device will be discussed. Preliminary results from the first...
Mr
Ray Yarema
(FNAL)
23/09/2009, 11:25
Packaging and interconnects
Oral
In 2008 a consortium of 15 international institutions was formed to pursue the development of 3D integrated circuits at a commercial foundry. The first MPW run from the consortium was submitted to Tezzaron. Wafers were fabricated at Chartered Semiconductor in the 130 nm process. These wafers were then assembled by Tezzaron into vertically integrated circuits. More than fifteen designs were...
Mrs
Stéphanie Godiot
(CPPM)
23/09/2009, 11:50
Packaging and interconnects
Oral
Facing the future challenges of hybrid pixel vertex detectors is foreseen to be done by microelectronic technology shrinking. However, this straightforward approach has some disadvantages in term of performances and cost. Based on a previous prototype of the future ATLAS pixel read-out chip FE-I4, this paper presents design and test of a hybrid pixel read-out chip using 3 dimensional...
Mr
Wojciech Dulinski
(IPHC, Strasbourg)
23/09/2009, 12:15
Packaging and interconnects
Oral
On the way towards fast, radiation tolerant and ultra thin CMOS sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). The proposed prototype device is a 245x245 pixel array with a pitch of 20 µm, In the first silicon layer charge sensing diode and the input buffer amplifiers are integrated, using 0.6 µm...
