21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

3D electronics for hybrid pixel detectors

23 Sept 2009, 11:50
25m
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Oral Packaging and interconnects Parallel Session B3 - Packaging and Interconnects

Speaker

Mrs Stéphanie Godiot (CPPM)

Description

Facing the future challenges of hybrid pixel vertex detectors is foreseen to be done by microelectronic technology shrinking. However, this straightforward approach has some disadvantages in term of performances and cost. Based on a previous prototype of the future ATLAS pixel read-out chip FE-I4, this paper presents design and test of a hybrid pixel read-out chip using 3 dimensional electronics technologies which enable to split pixel functionalities into two separate levels.

Summary

Hybrid silicon pixels detectors featuring high spatial resolution, very good signal to noise ratio and true two-dimensional information are currently used as vertex detectors in High Energy Physic experiments and especially in ATLAS and CMS detectors at the Large Hadron Collider (LHC).
Future requirements of post-LHC accelerators are, as usual, one step beyond the actual ones. Facing these new challenges could be addressed by 3D technologies which offer an alternative way of 2D shrinking with the advantages of technology mixing and cost effectiveness.
Starting from the FE_I4 prototype design (14×61 pixel matrix) in IBM 130 nm, which is a test pixel read-out chip for ATLAS upgrades, we developed 3D variants in Tezzaron-Chartered 130nm technology called FE_TC4.
In these variants, pixel functionalities are split into 2 levels (so-called tiers), the first one housing the analog pixel and sensor connections and the second one sheltering all digital related blocks. These two tiers are then connected face to face by copper bonds and the resulting pixel dimension before any real optimization was scaled down from 50×250µm to about 50×160µm.
One of these 3D circuits contains "special" digital blocks dedicated to the detailed study of the parasitic coupling between tiers, the other one has a more realistic digital design including the "4-pixel region" architecture which is foreseen for ATLAS pixel Front-End IC upgrades.
Silicon sensor has been also designed in order to address bump-bonding issues in this new type of chip stacks.
Design issues and complete tests results will be presented.

Primary author

Co-authors

Mr Abderrezak Mekkaoui (LBNL) Dr Alexander Rozanov (CPPM) Mr Benoît Chantepie (CPPM) Mr Denis Fougeron (CPPM) Dr Hans Krueger (University of Bonn) Mr Jean-Claude Clemens (CPPM) Mr Julien Fleury (LBNL) Dr Marlon Barbero (University of Bonn) Dr Maurice Garcia-Sciveres (LBNL) Mr Michael Karagounis (University of Bonn) Prof. Norbert Wermes (University of Bonn) Mr Patrick Pangaud (CPPM) Mr Richun Fei (CPPM) Mr Tomasz Hemperek (University of Bonn)

Presentation materials