Conveners
Parallel session A1 - ASICs
- Alessandro Marchioro (CERN)
Parallel session A1 - ASICs
- Christophe de La Taille (LAL Orsay)
Dr
Christine HU-GUO
(DRS-IPHC Strasbourg (IReS))
22/09/2009, 09:45
ASIC's
Oral
Designed and manufactured in a commercial CMOS 0.35 μm Opto process for equipping the EUDET beam telescope, MIMOSA-26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels of 576 rows and 1152 columns covering an active area of ~224 mm2. A single point resolution, better than 4 μm, is expected with a pixel pitch of 18.4 μm....
Thanushan Kugathasan
(INFN – Sezione di Torino, Università di Torino)
22/09/2009, 10:10
ASIC's
Oral
ToPix 2.0 is a prototype in a CMOS 0.13 μm technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI.
The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 μW/cell).
In an area of by 100 μm×100 μm each cell incorporates the...
Ms
Rebecca Coath
(STFC - Rutherford Appleton Laboratory)
22/09/2009, 11:00
ASIC's
Oral
We will present recent developments from two projects targeting advanced pixel architectures for scientific applications. Results will be reported from test structures demonstrating variants on a 4T pixel architecture. The variants include differences in pixel and diode size, the in-pixel source follower transistor size and the capacitance of the readout node to optimise for low noise and...
Mr
Francis Anghinolfi
(CERN)
22/09/2009, 11:25
ASIC's
Oral
We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25um technology and optimized for the short, 2.5cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We obtain the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in...
Dr
Ryo Ichimiya
(KEK)
22/09/2009, 11:50
ASIC's
Oral
A pixel sensor in 0.2um Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide in a monolithic chip, has many advantages. However, it has been found that applied electric field in the sensor layer also affects transistors in the adjacent circuit layer. Thus, full depletion voltage cannot be applied. To overcome...
Prof.
Wladyslaw Dabrowski
(Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, Al. Mickiewicza 30, 30-059 Cracow, Poland)
22/09/2009, 12:15
ASIC's
Oral
In this paper we present the preliminary experimental results obtained with 10 µm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/µm for a minimum ionizing particle, therefore a low noise, high gain and...
