21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

Session

Parallel session B2a - Production, testing and reliability

B2a
22 Sept 2009, 15:00
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Presentation materials

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  1. Mr Michal Dwuznik (Faculty of Physics and Applied Computer Science AGH Univeristy of Science and Technology)
    22/09/2009, 15:00
    Production, testing and reliability
    Oral
    A test system developed for ABCN-25 for ATLAS Inner Detector Upgrade is presented. The system presented is based on commercial off the shelf DAQ components by NI and foreseen to aid in chip characterization and module/hybrid development complementing full custom VME based setups. The key differences from the point of software development are presented, together with guidelines for developing...
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  2. Mr Carlos Abellan Beteta (Universidad de Barcelona-Unknown-Unknown)
    22/09/2009, 15:25
    Production, testing and reliability
    Oral
    An integrated test environment for the data acquisition electronics of the Scintillator Pad Detector (SPD) from the calorimeter of the LHCb experiment is presented. It allows to test separately every single board or to perform global system tests, while being able to emulate every part of the system and debug it. This environment is foreseen to test the production of spare electronics boards...
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  3. Mr Dominique Breton (Laboratoire de l'Accelerateur Lineaire (LAL/IN2P3/CNRS))
    22/09/2009, 15:50
    Production, testing and reliability
    Oral
    The currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The time resolution measured on the most advanced ASICs based on CFDs is of the order of 30 ps rms. TDC architectures are usually based either on a voltage ramp started or stopped by the digital pulse,...
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