10–14 Oct 2016
San Francisco Marriott Marquis
America/Los_Angeles timezone

FPGA based data processing in the ALICE High-Level Trigger in LHC Run 2

13 Oct 2016, 14:45
15m
Sierra A (San Francisco Mariott Marquis)

Sierra A

San Francisco Mariott Marquis

Oral Track 1: Online Computing Track 1: Online Computing

Speaker

Heiko Engel (Johann-Wolfgang-Goethe Univ. (DE))

Description

ALICE (A Large Ion Collider Experiment) is a detector system
optimized for the study of heavy ion collision detector at the
CERN LHC. The ALICE High Level Trigger (HLT) is a computing
cluster dedicated to the online reconstruction, analysis and
compression of experimental data. The High-Level Trigger receives
detector data via serial optical links into custom PCI-Express
based FPGA readout cards installed in the cluster machines. The
readout cards optionally process the data on a per-link level
already inside the FPGA and provide it to the host machines via
Direct Memory Access (DMA). The HLT data transport framework
collects the data from all machines and performs reconstruction,
analysis and compression with CPUs and GPUs as a distributed
application across the full cluster.

FPGA based data processing is enabled for the biggest detector of
ALICE, the Time Projection Chamber (TPC). TPC raw data is
processed in the FPGA with a hardware cluster finding algorithm
that is faster than a software implementation and saves a
significant amount of CPU resources in the HLT cluster. It also
provides some data reduction while introducing only a marginal
additional latency into the readout path. This algorithm is an
essential part of the HLT already since LHC Run 1 for both proton
and heavy ion runs. It was ported to the new HLT readout hardware
for Run 2, was improved for higher link rates and adjusted to the
recently upgraded TPC Readout Control Unit (RCU2). A flexible
firmware implementation allows both the old and the new TPC data
format and link rates to be handled transparently. Extended
protocol and data error detection, error handling and the
enhanced RCU2 data ordering scheme provide an improved physics
performance of the cluster finder.

This contribution describes the integration of the FPGA based
readout and processing into the HLT framework as well as the FPGA
based TPC cluster finding and its adoption to the changed readout
hardware during Run 2.

Primary Keyword (Mandatory) Data processing workflows and frameworks/pipelines
Secondary Keyword (Optional) DAQ
Tertiary Keyword (Optional) High performance computing

Primary author

Heiko Engel (Johann-Wolfgang-Goethe Univ. (DE))

Co-author

Torsten Alt (FIAS - Frankfurt Institute for Advanced Studies)

Presentation materials