CMS ECAL VFE phase II upgrade workshop

Contribution List

1. Welcome and Practical Details

marc besancon (cea-saclay/dapnia/spp)

12/05/2016, 09:00

Introduction

2. Goals of the workshop

Colin Jessop (University of Notre Dame (US))

12/05/2016, 09:20

Introduction

3. Overall Design and technical questions to answer

Marc Dejardin (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

12/05/2016, 09:40

Introduction

4. Engineering considerations

Magnus Hansen (CERN)

12/05/2016, 10:10

Introduction

5. VFE ASIC technical requirements

Marc Dejardin (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

12/05/2016, 14:00

VFE ASIC Design

6. TIA

Pascal Baron (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

12/05/2016, 15:00

VFE ASIC Design

17. ADC requirements and plans

Joao Varela (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

12/05/2016, 15:40

VFE ASIC Design

8. QIE

Jim Hirschauer (Fermi National Accelerator Lab. (US))

12/05/2016, 16:50

VFE ASIC Design

9. Discussion

12/05/2016, 17:30

VFE ASIC Design

21. MPGA++

Stephen Thomas (STFC - Rutherford Appleton Lab. (GB))

13/05/2016, 09:00

11. LVR Overview and interface to VFE

Werner Lustermann (Eidgenoessische Tech. Hochschule Zuerich (CH))

13/05/2016, 09:45

Other VFE design aspects (ADC/LVR/FE)

16. Tests of DC-DC converters

Patrizia Barria (University of Virginia (US))

13/05/2016, 10:10

Other VFE design aspects (ADC/LVR/FE)

12. VFE Board Design and Layout considerations

Werner Lustermann (Eidgenoessische Tech. Hochschule Zuerich (CH))

13/05/2016, 11:00

Other VFE design aspects (ADC/LVR/FE)

13. VFE interface to FE considerations

Alexander Singovski (University of Minnesota (US)), Alexandre Dolgopolov (Fermi National Accelerator Lab. (US))

13/05/2016, 11:20

Other VFE design aspects (ADC/LVR/FE)

18. Off detector electronics considerations

Bob Hirosky (University of Virginia (US))

13/05/2016, 11:40

Other VFE design aspects (ADC/LVR/FE)

14. Implications of fast timing to VFE board design

Francesco Micheli (Eidgenoessische Tech. Hochschule Zuerich (ETH))

13/05/2016, 12:00

Other VFE design aspects (ADC/LVR/FE)

15. Testbeam status and planning

Alexander Singovski (University of Minnesota (US))

13/05/2016, 12:20

Other VFE design aspects (ADC/LVR/FE)

20. MPGA++

Stephen Thomas (STFC - Rutherford Appleton Lab. (GB))

VFE ASIC Design