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CMS ECAL VFE phase II upgrade workshop

11–13 May 2016
CEA-Saclay INSTN
Europe/Zurich timezone

Session

VFE ASIC Design

12 May 2016, 14:00
112 (CEA-Saclay INSTN)

112

CEA-Saclay INSTN

Conveners

VFE ASIC Design

  • Marc Dejardin (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

Presentation materials

There are no materials yet.

  1. 5. VFE ASIC technical requirements
    Marc Dejardin (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
    12/05/2016, 14:00
  2. 6. TIA
    Pascal Baron (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
    12/05/2016, 15:00
  3. 17. ADC requirements and plans
    Joao Varela (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
    12/05/2016, 15:40
  4. 8. QIE
    Jim Hirschauer (Fermi National Accelerator Lab. (US))
    12/05/2016, 16:50
  5. 9. Discussion
    12/05/2016, 17:30
  6. 20. MPGA++
    Stephen Thomas (STFC - Rutherford Appleton Lab. (GB))
Building timetable...