CMS ECAL VFE phase II upgrade workshop

Session

VFE ASIC Design

12 May 2016, 14:00

112 (CEA-Saclay INSTN)

Conveners

VFE ASIC Design

• Marc Dejardin (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

5. VFE ASIC technical requirements

Marc Dejardin (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

12/05/2016, 14:00

6. TIA

Pascal Baron (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

12/05/2016, 15:00

17. ADC requirements and plans

Joao Varela (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

12/05/2016, 15:40

8. QIE

Jim Hirschauer (Fermi National Accelerator Lab. (US))

12/05/2016, 16:50

9. Discussion

12/05/2016, 17:30

20. MPGA++

Stephen Thomas (STFC - Rutherford Appleton Lab. (GB))