21st IEEE Real Time Conference - Colonial Williamsburg

A new all-digital background calibration technique for time-interleaved ADC using first order approximation FIR filters

14 Jun 2018, 14:35

1h 30m

Woodlands Conference Center

Poster presentation Real Time System Architectures and Intelligent Signal Processing Poster 2

Speaker

Mr Jiadong Hu (State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China ;Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China)

Description

This paper describes a new all-digital technique for calibration of the mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce the circuit area. The proposed technique employ first order approximation FIR filter banks, which do not need large number of FIR taps. In case of a four-channel 12-bit TIADC, the proposed technique improves SINAD of simulated data from 54dB to 61dB, and improves SINAD of measured data from 49dB to 53dB, while the number of FIR taps is only 31. In the case of slight mismatches, 22-bit FIR coefficient is sufficient to correct 12-bit signals, which makes it easy to implement this technique in hardware. In addition, this technique is not limited by the number of sub-ADC channels and is also suitable for wideband signals.

Presentation materials

A New All-Digital Background Calibration Technique for Time-Interleaved ADC Using First Order Approximation FIR Filters

PO_PosterSession2_416.pdf