4th Summer School on INtelligent signal processing for FrontIEr Research and Industry

VHDL for beginners and for medium knowledge people

Not scheduled

7m

Abraão de Moraes Auditorium (IF) (Campus of USP in Sao Paulo)

Presentation of the Laboratories

Speaker

Prof. Wang (POLI-USP)

Description

This Lab will comprise two parts of 3h each thus the non beginners can go immediately to the second part (medium knowledge)