The 130nm CMOS node is the technology of choice for the design of ASICs for many current state-of-the art vertex detectors and for future trackers at high luminosity experiments. This technology is chosen among other reasons for its radiation hardness. Experience with 130nm ASICs in ongoing experiments shows however that leakage current of NMOS transistors at low doses can lead to a substantial increase of the chip current with potentially severe consequences on the entire detector system.
The ATLAS ITK strip detector for the HL-LHC employs this technology for the design of on-stave readout and control chips. The 130nm chip set is made of the strips readout chip, the so-called ATLAS Binary Chip (ABCStar), the Hybrid Controller Chip (HCCStar) to interface the ABC chips to the service bus, and the Autonomous Monitor and Control Chip (AMAC) providing both monitoring and interrupt functionality. A thorough characterisation of the total ionising dose (TID) effects on the parameters of the chips needs to be carried out to estimate the current increase as a function of dose and temperature. This allows the development of models to predict the electronics power consumption during operation and to design a detector system able to cope with the change in current over the experiment lifetime.
The talk will introduce the ABCStar, HCCStar and AMAC chips, and review the effects of TID on 130nm CMOS technologies. Results of irradiations with gamma rays and protons of the ASICs prototypes will be presented, and the model of power increase as function of temperature and dose will be discussed.