12th "Trento" Workshop on Advanced Silicon Radiation Detectors

Session

Session 6: Electronics

Electronics

21 Feb 2017, 11:15

Aula Grande (FBK, Trento)

Conveners

Session 6: Electronics

• Nicolo Cartiglia (Universita e INFN Torino (IT))

9. Silicon Drift Detectors and readout ASICs for High-Resolution and High-Count Rate X-ray Spectroscopy

Mr Giovanni Bellotti (Politecnico di Milano - INFN Milano)

21/02/2017, 11:15

Oral

This work presents the progress done in the development of multichannel X-Ray detectors based on Silicon Drift Detectors matrices and related readout ASICs.
SDDs allow to achieve state of the art performances for high-resolution and high-count rate spectroscopy. CUBE preamplifier [1] allows to reach optimal resolution performances even at high count rate i.e. at short pulse processing times....

18. ATLAS ITK strips ASIC: design and radiation hardness

Laura Gonella (University of Birmingham (UK)), On behalf of the ATLAS ITK strips ASICs working group

21/02/2017, 11:35

Oral

The 130nm CMOS node is the technology of choice for the design of ASICs for many current state-of-the art vertex detectors and for future trackers at high luminosity experiments. This technology is chosen among other reasons for its radiation hardness. Experience with 130nm ASICs in ongoing experiments shows however that leakage current of NMOS transistors at low doses can lead to a...

30. TOFFEE a fully custom readout ASIC for timing applications with UFSD

Mr Elias Jonhatan Olave (Politecnico di Torino - INFN Torino)

21/02/2017, 11:55

Oral

Time tagging is becoming a fundamental tool for the future of High Energy Physics, where the high luminosity will introduce hundreds of overlapping events (pile-up) making really tricky to take and analyse data. This is the case of the high luminosity LHC, where the expected number of events per bunch crossing is ~150-200. A possible strategy for pile-up mitigation consists in exploit time...

42. Results from CHIPIX65 prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC experiments

Luca Pacher (Universita e INFN Torino (IT))

21/02/2017, 12:15

Oral

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is of 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue very-front-end designs, one synchronous and one asynchronous,...