Speaker
Description
Due to their capability to integrate the readout electronics on the sensor substrate while providing fast charge collection by drift and high radiation tolerance levels of 10E15 neq/cm2, High Voltage-CMOS (HV-CMOS) detectors are being developed for their use or potential use in particle physics applications such as the Mu3e experiment, the ATLAS ITk upgrade and CLIC. Despite their fast charge collection, HV-CMOS detectors cannot supply the extremely accurate signal arrival times required by these applications as there exist charge collection time uncertainties and time-walk variations. Charge collection time uncertainties are given by the different times the charge needs to reach the collecting electrodes as a function of its generation point, whereas time-walk variations appear between the detection of small and large signals as the response time of the readout electronics is dependent on the signal strength. Charge collection time uncertainties are minimized with large sensor bias voltages. A few time-walk mitigation techniques have already been integrated in prototype HV-CMOS ASICs, such as time-walk compensating comparators, multiple threshold comparators and sampling circuits. However, these solutions often come at the expenses of needing more time for the detection or presenting limited efficiency.
This contribution describes the status of the design of an R&D HV-CMOS ASIC within the RD50 collaboration aimed mostly at improving the timing resolution of the detector using different solutions at the readout circuit level. Given its advantages in terms of isolation layers to embed CMOS electronics inside the pixel area, high number of metal layers for routing, backside biasing, stitching options and cost-efficient prototyping, the technology chosen for this ASIC is the 150 nm node from LFoundry. In this talk, I will review our current experience with LFoundry and provide details about the submission. The ASIC contains a few different matrices of HV-CMOS pixels with front-end electronics that improve the timing resolution of the detector. These electronics are based on the utilization of an analog sampling circuit, a Time-to-Digital Converter (TDC) and a super-fast amplifier. The ASIC also integrates circuits for studying new sensor cross-sections and pre-stitching options, as well as test structures. More information will be given at the workshop.
