10-15 March 2019
Steinmatte conference center
Europe/Zurich timezone

Primary Vertex Reconstruction with Deep Learning in FPGAs for the Phase-2 Upgrade of the Level-1 Trigger of CMS

Not scheduled
Steinmatte conference center

Steinmatte conference center

Hotel Allalin, Saas Fee, Switzerland https://allalin.ch/conference/
Oral Track 2: Data Analysis - Algorithms and Tools Track 2: Data Analysis - Algorithms and Tools


Antoni Shtipliyski (Imperial College (GB))


The High-Luminosity upgrade of LHC (HL-LHC) is expected to deliver a total luminosity of 3000 fb$^{-1}$ to the general purpose experiments. This will allow the measurement of Standard Model processes with unprecedented precision, and will significantly increase the reach of searches for new physics. Higher data rates and increased radiation levels will require substantial upgrades to the detectors and their trigger and data acquisition systems. The Phase-2 upgrade of CMS comprises a complete replacement of the silicon tracker that will for the first time provide tracking information to the Level-1 (L1) hardware trigger. The upgraded trigger is designed to reduce the event rate to 750 kHz from a collision frequency of 40 MHz by processing 50 Tbps of incoming bandwidth within 12.5 $\mu$s latency. The increased luminosity is expected to produce around 200 additional “pileup” interactions per bunch crossing. This creates a challenging environment for efficient triggering and the use of tracks in the L1 algorithms would be essential for pileup mitigation, since charged particle tracks can be matched to energy deposits in the calorimeters and tracks in the muon detectors to identify directly the particles originating from the primary interaction vertex of the hard scatter process. This talk will introduce the challenges involved in reconstructing the primary vertex at L1 and describe a Deep Learning algorithm developed for inference in an FPGA data processor. The stringent time requirements of the L1 trigger mandate that vertex reconstruction is done within O(100ns) while the computing technology poses the novel problem of balancing the trade-off between algorithm sophistication and FPGA resource usage/latency. Preliminary plans for operating the algorithm during data-taking will also be outlined.

Primary author

Antoni Shtipliyski (Imperial College (GB))

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