Name: How to do ultrafast Deep Neural Network inference on FPGAs
Start: 2019-02-06T08:30:00+01:00
End: 2019-02-06T18:00:00+01:00
Location: University of Zurich, Campus Irchel

How to do ultrafast Deep Neural Network inference on FPGAs

Wednesday 6 February 2019 - 08:30
University of Zurich, Campus Irchel (Y16-G-15)

: Sessions

: Talks

: Breaks

6 Feb 2019

08:30	Registration (Y16-G-15)
09:00	Welcome - Thea Aarrestad (Universitaet Zuerich (CH)) (Y16-G-15) AWScloud.pdf FPGA4HEP.pdf
09:15	What is HLS4ML? - Jennifer Ngadiuba (CERN) (Y16-G-15)
10:30	--- Coffee break ---
11:00	Firmware implementation with SDAccel (Y16-G-15)

12:00	--- Lunch break ---
13:30	Optimize FPGA design: quantization and parallelization with HLS4ML - Jennifer Ngadiuba (CERN) (Y16-G-15)
14:30	Optimize FPGA design: model compression (Y16-G-15)
15:30	--- Coffee break ---
16:00	Model acceleration on cloud FPGAs - Jennifer Ngadiuba (CERN) (Y16-G-15)

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