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How to do ultrafast Deep Neural Network inference on FPGAs

Wednesday, February 6, 2019 - 8:30 AM
University of Zurich, Campus Irchel (Y16-G-15)

        : Sessions
    /     : Talks
        : Breaks
Feb 6, 2019
AM
8:30 AM Registration   (Y16-G-15)
9:00 AM Welcome - Thea Aarrestad (Universitaet Zuerich (CH))   (Y16-G-15)
9:15 AM What is HLS4ML? - Jennifer Ngadiuba (CERN)   (Y16-G-15)
10:30 AM --- Coffee break ---
11:00 AM Firmware implementation with SDAccel   (Y16-G-15)
PM
12:00 PM --- Lunch break ---
1:30 PM Optimize FPGA design: quantization and parallelization with HLS4ML - Jennifer Ngadiuba (CERN)   (Y16-G-15)
2:30 PM Optimize FPGA design: model compression   (Y16-G-15)
3:30 PM --- Coffee break ---
4:00 PM Model acceleration on cloud FPGAs - Jennifer Ngadiuba (CERN)   (Y16-G-15)