How to do ultrafast Deep Neural Network inference on FPGAs

Europe/Zurich
Y16-G-15 (University of Zurich, Campus Irchel)

Y16-G-15

University of Zurich, Campus Irchel

Physik Institut, UZH Building 16/36 (entrance for both is building 36) Winterthurerstrasse 190 8057 Zurich
Dylan Sheldon Rankin (Massachusetts Inst. of Technology (US)), Jennifer Ngadiuba (CERN), Thea Aarrestad (Universitaet Zuerich (CH))
Description

A key component in autonomous vehicle and fast triggering systems, learn how FPGAs do real-time DNN inference in this hands-on course. Topics include: 

  • Model compression and quantization
  • High-level synthesis
  • Firmware implementation
  • Model acceleration on cloud FPGAs

The class is given by Dr. Jennifer Ngadiuba (CERN) and Dr. Dylan Rankin (MIT) and consists of half a day of lectures as well as a hands-on sessions.

You'll learn how to compress and synthesise your own TensorFlow model, as well as implement it on a Xilinx FPGA on the Amazon cloud. 

The course is targeted at PhD, Postdocs and Professors, but others will be allowed to participate if there are available places. 

The lectures and hands-on session will take place at the UZH Irchel Campus in the Physik Institut (building 36)

 

All course material can be found as attachments to the timetable, or at

https://github.com/FPGA4HEP/course_material 

Upload your plot here:

https://cernbox.cern.ch/index.php/s/70rnEFKLh4dU37m


Organizers:
Thea Aarrestad (UZH)
Jennifer Ngadiuba (CERN)

Dylan Rankin (MIT)
Maurizio Pierini (CERN)

Ben Kilminster (UZH)

Participants
  • Alberto Zucchetta
  • Alessandro Manfredini
  • Alexander Malafeev
  • Alexey Gronskiy
  • Alvaro Lopez Garcia
  • Anatolii Evseev
  • Andre Sznajder
  • Andrea Bettati
  • Andres Upegui
  • Arash Jofrehei
  • Ashraf Mohamed
  • Balint Radics
  • Ben Carlson
  • Ben Kilminster
  • Carlos Abellan Beteta
  • Chiara Capelli
  • Cristiano Sebastiani
  • Daniel Krefl
  • Daniel Spitzbart
  • Daniela Schaefer
  • Daniele Bonacorsi
  • Davide Valsecchi
  • Dejan Golubovic
  • Dionysios Diamantopoulos
  • Dylan Sheldon Rankin
  • Ekaterina Kuznetsova
  • Francisco Yumiceva
  • Gabriel Facini
  • Gabriel Palacino
  • Gael Touquet
  • Gian Michele Innocenti
  • Guillermo Jose Loustau De Linares
  • Harleen Hanspal
  • Hualin Mei
  • Huilin Qu
  • Iacopo Longarini
  • Iaroslava Bezshyiko
  • Iordan Doytchinov
  • Jennifer Ngadiuba
  • Jeremiah Harmsen
  • Joao Vitor Viana Barbosa
  • Joerg Stelzer
  • Johannes Martin Wuthrich
  • Jonas Eschle
  • Jory Sonneveld
  • Karol Hennessy
  • Kim Albertsson
  • Klaus-Ulrich Miltenberger
  • Krunal Bipin Gedia
  • Lars Gerchow
  • Leonardo Cristella
  • Loriano Storchi
  • Lucas Santiago Borgna
  • Luigi Sabetta
  • Lukas Arnold
  • Lukasz Janyst
  • Lukasz Kreczko
  • Manuel Rodriguez
  • Manuel Sommerhalder
  • Marco Pocaterra
  • Marko Jerčić
  • Michael Aaron Kagan
  • Miles Timpe
  • Mirko Mariotti
  • Miroslaw Marszalek
  • Mitra Purandare
  • Nadezda Chernyavskaya
  • Nadir Daci
  • Nikola Poljak
  • Owen Colegrove
  • Philip Chang
  • Pieter Everaerts
  • Pinar Ezgi Çöl
  • Prasenjit Saha
  • Ralf Erik Rossel
  • René BEUCHAT
  • Riccardo Travaglini
  • Sascha Liechti
  • Sebastian Templ
  • Serena Farina
  • Simone Francescato
  • Stefano Carrazza
  • Stefano Giagu
  • Stephane Cooperstein
  • Steven Lee
  • Thea Aarrestad
  • Thomas Owen James
  • Tommaso Diotalevi
  • Vadym Denysenko
  • Valentin Y Kuznetsov
  • Varun Nagpal
  • Vladimir Loncar
  • Wendi Deng
  • Wolfgang Waltenberger
  • Yanina Biondi
    • 08:30 09:00
      Registration 30m
    • 09:00 09:15
      Welcome 15m
      Speaker: Thea Aarrestad (Universitaet Zuerich (CH))
    • 09:15 10:30
      What is HLS4ML? 1h 15m

      An introduction to the HLS4ML framework

      Speaker: Jennifer Ngadiuba (CERN)
    • 10:30 11:00
      Coffee break 30m
    • 11:00 12:00
      Firmware implementation with SDAccel 1h

      Export HLS design to firmware with Xilinx SDAccel on Amazon cloud.

    • 12:00 13:30
      Lunch break 1h 30m
    • 13:30 14:30
      Optimize FPGA design: quantization and parallelization with HLS4ML 1h
      Speaker: Jennifer Ngadiuba (CERN)
    • 14:30 15:30
      Optimize FPGA design: model compression 1h
    • 15:30 16:00
      Coffee break 30m
    • 16:00 17:00
      Model acceleration on cloud FPGAs 1h
      Speaker: Jennifer Ngadiuba (CERN)