How to do ultrafast Deep Neural Network inference on FPGAs

Europe/Zurich
Y16-G-15 (University of Zurich, Campus Irchel)

Y16-G-15

University of Zurich, Campus Irchel

Physik Institut, UZH Building 16/36 (entrance for both is building 36) Winterthurerstrasse 190 8057 Zurich
Dylan Sheldon Rankin (Massachusetts Inst. of Technology (US)), Jennifer Ngadiuba (CERN), Thea Aarrestad (Universitaet Zuerich (CH))
Description

A key component in autonomous vehicle and fast triggering systems, learn how FPGAs do real-time DNN inference in this hands-on course. Topics include: 

  • Model compression and quantization
  • High-level synthesis
  • Firmware implementation
  • Model acceleration on cloud FPGAs

The class is given by Dr. Jennifer Ngadiuba (CERN) and Dr. Dylan Rankin (MIT) and consists of half a day of lectures as well as a hands-on sessions.

You'll learn how to compress and synthesise your own TensorFlow model, as well as implement it on a Xilinx FPGA on the Amazon cloud. 

The course is targeted at PhD, Postdocs and Professors, but others will be allowed to participate if there are available places. 

The lectures and hands-on session will take place at the UZH Irchel Campus in the Physik Institut (building 36)

 

All course material can be found as attachments to the timetable, or at

https://github.com/FPGA4HEP/course_material 

Upload your plot here:

https://cernbox.cern.ch/index.php/s/70rnEFKLh4dU37m


Organizers:
Thea Aarrestad (UZH)
Jennifer Ngadiuba (CERN)

Dylan Rankin (MIT)
Maurizio Pierini (CERN)

Ben Kilminster (UZH)

Participants
    • 1
      Registration
    • 2
      Welcome
      Speaker: Thea Aarrestad (Universitaet Zuerich (CH))
    • 3
      What is HLS4ML?

      An introduction to the HLS4ML framework

      Speaker: Jennifer Ngadiuba (CERN)
    • 10:30
      Coffee break
    • 4
      Firmware implementation with SDAccel

      Export HLS design to firmware with Xilinx SDAccel on Amazon cloud.

    • 12:00
      Lunch break
    • 5
      Optimize FPGA design: quantization and parallelization with HLS4ML
      Speaker: Jennifer Ngadiuba (CERN)
    • 6
      Optimize FPGA design: model compression
    • 15:30
      Coffee break
    • 7
      Model acceleration on cloud FPGAs
      Speaker: Jennifer Ngadiuba (CERN)